Architecture specific initialization prior to processor structures initialization

sdk/xtdk/amd64/arfuncs.h

@@ -95,6 +95,10 @@ VOID
 ArWriteControlRegister(IN USHORT ControlRegister,
                        IN UINT_PTR Value);
 
+XTCDECL
+VOID
+ArWriteEflagsRegister(IN UINT_PTR Value);
+
 XTCDECL
 VOID
 ArWriteModelSpecificRegister(IN ULONG Register,

sdk/xtdk/amd64/artypes.h

@@ -75,6 +75,13 @@
 #define X86_MSR_GSBASE                                  0xC0000101
 #define X86_MSR_KERNEL_GSBASE                           0xC0000102
 
+/* Processor features in the EFER MSR */
+#define X86_MSR_EFER_SCE                                (1 <<  0)
+#define X86_MSR_EFER_LME                                (1 <<  8)
+#define X86_MSR_EFER_LMA                                (1 << 10)
+#define X86_MSR_EFER_NXE                                (1 << 11)
+#define X86_MSR_EFER_SVME                               (1 << 12)
+
 /* CPUID features enumeration list */
 typedef enum _CPUID_FEATURES
 {

sdk/xtdk/i686/arfuncs.h

@@ -91,6 +91,10 @@ VOID
 ArWriteControlRegister(IN USHORT ControlRegister,
                        IN UINT_PTR Value);
 
+XTCDECL
+VOID
+ArWriteEflagsRegister(IN UINT_PTR Value);
+
 XTCDECL
 VOID
 ArWriteModelSpecificRegister(IN ULONG Register,

xtoskrnl/ar/amd64/cpufunc.c

@@ -526,6 +526,26 @@ ArWriteControlRegister(IN USHORT ControlRegister,
     }
 }
 
+/**
+ * Writes the specified value to the program status and control (EFLAGS) register.
+ *
+ * @param Value
+ *        The value to write to the EFLAGS register.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArWriteEflagsRegister(IN UINT_PTR Value)
+{
+    asm volatile("push %0\n"
+                 "popf"
+                 :
+                 : "rim" (Value));
+}
+
 /**
  * Writes a 64-bit value to the requested Model Specific Register (MSR).
  *

xtoskrnl/ar/i686/cpufunc.c

@@ -487,6 +487,26 @@ ArWriteControlRegister(IN USHORT ControlRegister,
     }
 }
 
+/**
+ * Writes the specified value to the program status and control (EFLAGS) register.
+ *
+ * @param Value
+ *        The value to write to the EFLAGS register.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArWriteEflagsRegister(IN UINT_PTR Value)
+{
+    asm volatile("push %0\n"
+                 "popf"
+                 :
+                 : "rim" (Value));
+}
+
 /**
  * Writes a 64-bit value to the requested Model Specific Register (MSR).
  *

xtoskrnl/ke/amd64/krnlinit.c

@@ -20,6 +20,21 @@ XTAPI
 VOID
 KepArchInitialize(VOID)
 {
+    /* Enable global paging support */
+    ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PGE);
+
+    /* Enable write-protection */
+    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
+
+    /* Set alignment mask */
+    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_AM);
+
+    /* Re-enable IDE interrupts */
+    HlIoPortOutByte(0x376, 0);
+    HlIoPortOutByte(0x3F6, 0);
+
+    /* Set system call extensions (SCE) flag in EFER MSR */
+    ArWriteModelSpecificRegister(X86_MSR_EFER, ArReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
 }
 
 /**

xtoskrnl/ke/i686/krnlinit.c

@@ -20,6 +20,15 @@ XTAPI
 VOID
 KepArchInitialize(VOID)
 {
+    /* Clear EFLAGS register */
+    ArWriteEflagsRegister(0);
+
+    /* Enable write-protection */
+    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
+
+    /* Re-enable IDE interrupts */
+    HlIoPortOutByte(0x376, 0);
+    HlIoPortOutByte(0x3F6, 0);
 }
 
 /**

xtoskrnl/ke/krnlinit.c

@@ -49,12 +49,12 @@ KeStartXtSystem(IN PKERNEL_INITIALIZATION_BLOCK Parameters)
     /* Initialize kernel stacks */
     KepInitializeStack(Parameters);
 
-    /* Initialize boot CPU */
-    ArInitializeProcessor();
-
     /* Architecture specific initialization */
     KepArchInitialize();
 
+    /* Initialize boot CPU */
+    ArInitializeProcessor();
+
     /* Switch boot stack alligning it to 4 byte boundary */
     KepSwitchBootStack(KeInitializationBlock->KernelBootStack & ~0x3);
 }