forked from xt-sys/exectos
Implement basic APIC support, including X2APIC
This commit is contained in:
@@ -17,7 +17,8 @@
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/* APIC base addresses */
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#define APIC_BASE 0xFFFFFFFFFFFE0000
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#define APIC_MSR_BASE 0x0000001B
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#define APIC_LAPIC_MSR_BASE 0x0000001B
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#define APIC_X2APIC_MSR_BASE 0x00000800
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/* APIC vector definitions */
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#define APIC_VECTOR_ZERO 0x00
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@@ -69,4 +70,52 @@
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/* Serial port I/O addresses */
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#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
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/* APIC Base Register */
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typedef union _APIC_BASE_REGISTER
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{
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ULONGLONG LongLong;
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struct
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{
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ULONGLONG Reserved1:8;
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ULONGLONG BootStrapProcessor:1;
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ULONGLONG Reserved2:1;
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ULONGLONG ExtendedMode:1;
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ULONGLONG Enable:1;
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ULONGLONG BaseAddress:40;
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ULONGLONG Reserved3:12;
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};
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} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
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/* APIC Local Vector Table (LVT) Register */
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typedef union _APIC_LVT_REGISTER
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG MessageType:3;
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ULONG Reserved1:1;
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ULONG DeliveryStatus:1;
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ULONG Reserved2:1;
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ULONG RemoteIRR:1;
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ULONG TriggerMode:1;
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ULONG Mask:1;
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ULONG TimerMode:1;
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ULONG Reserved3:13;
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};
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} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
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/* APIC Spurious Register */
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typedef union _APIC_SPURIOUS_REGISTER
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG SoftwareEnable:1;
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ULONG CoreChecking:1;
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ULONG Reserved:22;
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};
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} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
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#endif /* __XTDK_AMD64_HLTYPES_H */
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@@ -101,14 +101,14 @@ typedef enum _APIC_REGISTER
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APIC_EOI = 0x0B, /* EOI Register */
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APIC_RRR = 0x0C, /* Remote Read Register */
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APIC_LDR = 0x0D, /* Logical Destination Register */
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APIC_DFR = 0x0E, /* Destination Format Register */
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APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
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APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
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APIC_ISR = 0x10, /* Interrupt Service Register*/
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APIC_TMR = 0x18, /* Trigger Mode Register */
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APIC_IRR = 0x20, /* Interrupt Request Register */
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APIC_ESR = 0x28, /* Error Status Register */
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APIC_ICR0 = 0x30, /* Interrupt Command Register */
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APIC_ICR1 = 0x31, /* Interrupt Command Register */
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APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
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APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
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APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
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APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
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@@ -127,6 +127,13 @@ typedef enum _APIC_REGISTER
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APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
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} APIC_REGISTER, *PAPIC_REGISTER;
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/* APIC mode list */
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typedef enum _HAL_APIC_MODE
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{
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APIC_MODE_COMPAT,
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APIC_MODE_X2APIC
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} HAL_APIC_MODE, *PHAL_APIC_MODE;
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/* Serial (COM) port initial state */
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typedef struct _CPPORT
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{
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@@ -17,7 +17,8 @@
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/* APIC base addresses */
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#define APIC_BASE 0xFFFE0000
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#define APIC_MSR_BASE 0x0000001B
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#define APIC_LAPIC_MSR_BASE 0x0000001B
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#define APIC_X2APIC_MSR_BASE 0x00000800
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/* APIC vector definitions */
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#define APIC_VECTOR_ZERO 0x00
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@@ -74,4 +75,52 @@
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/* Serial port I/O addresses */
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#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
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/* APIC Base Register */
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typedef union _APIC_BASE_REGISTER
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{
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ULONGLONG LongLong;
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struct
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{
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ULONGLONG Reserved1:8;
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ULONGLONG BootStrapProcessor:1;
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ULONGLONG Reserved2:1;
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ULONGLONG ExtendedMode:1;
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ULONGLONG Enable:1;
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ULONGLONG BaseAddress:40;
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ULONGLONG Reserved3:12;
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};
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} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
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/* APIC Local Vector Table (LVT) Register */
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typedef union _APIC_LVT_REGISTER
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG MessageType:3;
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ULONG Reserved1:1;
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ULONG DeliveryStatus:1;
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ULONG Reserved2:1;
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ULONG RemoteIRR:1;
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ULONG TriggerMode:1;
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ULONG Mask:1;
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ULONG TimerMode:1;
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ULONG Reserved3:13;
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};
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} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
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/* APIC Spurious Register */
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typedef union _APIC_SPURIOUS_REGISTER
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG SoftwareEnable:1;
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ULONG CoreChecking:1;
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ULONG Reserved:22;
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};
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} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
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#endif /* __XTDK_I686_HLTYPES_H */
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