Implement basic APIC support, including X2APIC

This commit is contained in:
2023-11-27 22:38:15 +01:00
parent 4ca4e298f0
commit e5adc31af7
7 changed files with 307 additions and 8 deletions

View File

@@ -17,7 +17,8 @@
/* APIC base addresses */
#define APIC_BASE 0xFFFFFFFFFFFE0000
#define APIC_MSR_BASE 0x0000001B
#define APIC_LAPIC_MSR_BASE 0x0000001B
#define APIC_X2APIC_MSR_BASE 0x00000800
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
@@ -69,4 +70,52 @@
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
/* APIC Base Register */
typedef union _APIC_BASE_REGISTER
{
ULONGLONG LongLong;
struct
{
ULONGLONG Reserved1:8;
ULONGLONG BootStrapProcessor:1;
ULONGLONG Reserved2:1;
ULONGLONG ExtendedMode:1;
ULONGLONG Enable:1;
ULONGLONG BaseAddress:40;
ULONGLONG Reserved3:12;
};
} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
/* APIC Local Vector Table (LVT) Register */
typedef union _APIC_LVT_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG MessageType:3;
ULONG Reserved1:1;
ULONG DeliveryStatus:1;
ULONG Reserved2:1;
ULONG RemoteIRR:1;
ULONG TriggerMode:1;
ULONG Mask:1;
ULONG TimerMode:1;
ULONG Reserved3:13;
};
} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
/* APIC Spurious Register */
typedef union _APIC_SPURIOUS_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG SoftwareEnable:1;
ULONG CoreChecking:1;
ULONG Reserved:22;
};
} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
#endif /* __XTDK_AMD64_HLTYPES_H */

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@@ -101,14 +101,14 @@ typedef enum _APIC_REGISTER
APIC_EOI = 0x0B, /* EOI Register */
APIC_RRR = 0x0C, /* Remote Read Register */
APIC_LDR = 0x0D, /* Logical Destination Register */
APIC_DFR = 0x0E, /* Destination Format Register */
APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
APIC_ISR = 0x10, /* Interrupt Service Register*/
APIC_TMR = 0x18, /* Trigger Mode Register */
APIC_IRR = 0x20, /* Interrupt Request Register */
APIC_ESR = 0x28, /* Error Status Register */
APIC_ICR0 = 0x30, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
@@ -127,6 +127,13 @@ typedef enum _APIC_REGISTER
APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
} APIC_REGISTER, *PAPIC_REGISTER;
/* APIC mode list */
typedef enum _HAL_APIC_MODE
{
APIC_MODE_COMPAT,
APIC_MODE_X2APIC
} HAL_APIC_MODE, *PHAL_APIC_MODE;
/* Serial (COM) port initial state */
typedef struct _CPPORT
{

View File

@@ -17,7 +17,8 @@
/* APIC base addresses */
#define APIC_BASE 0xFFFE0000
#define APIC_MSR_BASE 0x0000001B
#define APIC_LAPIC_MSR_BASE 0x0000001B
#define APIC_X2APIC_MSR_BASE 0x00000800
/* APIC vector definitions */
#define APIC_VECTOR_ZERO 0x00
@@ -74,4 +75,52 @@
/* Serial port I/O addresses */
#define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
/* APIC Base Register */
typedef union _APIC_BASE_REGISTER
{
ULONGLONG LongLong;
struct
{
ULONGLONG Reserved1:8;
ULONGLONG BootStrapProcessor:1;
ULONGLONG Reserved2:1;
ULONGLONG ExtendedMode:1;
ULONGLONG Enable:1;
ULONGLONG BaseAddress:40;
ULONGLONG Reserved3:12;
};
} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
/* APIC Local Vector Table (LVT) Register */
typedef union _APIC_LVT_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG MessageType:3;
ULONG Reserved1:1;
ULONG DeliveryStatus:1;
ULONG Reserved2:1;
ULONG RemoteIRR:1;
ULONG TriggerMode:1;
ULONG Mask:1;
ULONG TimerMode:1;
ULONG Reserved3:13;
};
} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
/* APIC Spurious Register */
typedef union _APIC_SPURIOUS_REGISTER
{
ULONG Long;
struct
{
ULONG Vector:8;
ULONG SoftwareEnable:1;
ULONG CoreChecking:1;
ULONG Reserved:22;
};
} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
#endif /* __XTDK_I686_HLTYPES_H */