Code formatting

This commit is contained in:
2023-01-05 22:45:52 +01:00
parent 2920c1042a
commit f2b51ff69c
2 changed files with 26 additions and 22 deletions

View File

@@ -43,7 +43,9 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers)
asm volatile("cpuid" asm volatile("cpuid"
: "=a" (MaxLeaf) : "=a" (MaxLeaf)
: "a" (Registers->Leaf & 0x80000000) : "a" (Registers->Leaf & 0x80000000)
: "rbx", "rcx", "rdx"); : "rbx",
"rcx",
"rdx");
/* Check if CPU supports this command */ /* Check if CPU supports this command */
if(Registers->Leaf > MaxLeaf) if(Registers->Leaf > MaxLeaf)
@@ -55,11 +57,11 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers)
/* Execute CPUID function */ /* Execute CPUID function */
asm volatile("cpuid" asm volatile("cpuid"
: "=a" (Registers->Eax), : "=a" (Registers->Eax),
"=b" (Registers->Ebx), "=b" (Registers->Ebx),
"=c" (Registers->Ecx), "=c" (Registers->Ecx),
"=d" (Registers->Edx) "=d" (Registers->Edx)
: "a" (Registers->Leaf), : "a" (Registers->Leaf),
"c" (Registers->SubLeaf)); "c" (Registers->SubLeaf));
/* Return TRUE */ /* Return TRUE */
return TRUE; return TRUE;
@@ -183,7 +185,7 @@ HlIoPortOutByte(IN USHORT Port,
asm volatile("outb %0, %1" asm volatile("outb %0, %1"
: :
: "a"(Value), : "a"(Value),
"Nd"(Port)); "Nd"(Port));
} }
/** /**
@@ -207,7 +209,7 @@ HlIoPortOutShort(IN USHORT Port,
asm volatile("outw %0, %1" asm volatile("outw %0, %1"
: :
: "a"(Value), : "a"(Value),
"Nd"(Port)); "Nd"(Port));
} }
/** /**
@@ -231,7 +233,7 @@ HlIoPortOutLong(IN USHORT Port,
asm volatile("outl %0, %1" asm volatile("outl %0, %1"
: :
: "a"(Value), : "a"(Value),
"Nd"(Port)); "Nd"(Port));
} }
/** /**
@@ -315,7 +317,7 @@ HlReadModelSpecificRegister(IN ULONG Register)
asm volatile("rdmsr" asm volatile("rdmsr"
: "=a"(Low), : "=a"(Low),
"=d"(High) "=d"(High)
: "c"(Register)); : "c"(Register));
return ((ULONGLONG)High << 32) | Low; return ((ULONGLONG)High << 32) | Low;
@@ -335,8 +337,8 @@ HlReadTimeStampCounter()
ULONGLONG Low, High; ULONGLONG Low, High;
asm volatile("rdtsc" asm volatile("rdtsc"
:"=a"(Low), : "=a"(Low),
"=d"(High)); "=d"(High));
return ((ULONGLONG)High << 32) | Low; return ((ULONGLONG)High << 32) | Low;
} }
@@ -438,6 +440,6 @@ HlWriteModelSpecificRegister(IN ULONG Register,
asm volatile("wrmsr" asm volatile("wrmsr"
: :
: "c"(Register), : "c"(Register),
"a"(Low), "a"(Low),
"d"(High)); "d"(High));
} }

View File

@@ -43,7 +43,9 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers)
asm volatile("cpuid" asm volatile("cpuid"
: "=a" (MaxLeaf) : "=a" (MaxLeaf)
: "a" (Registers->Leaf & 0x80000000) : "a" (Registers->Leaf & 0x80000000)
: "rbx", "rcx", "rdx"); : "rbx",
"rcx",
"rdx");
/* Check if CPU supports this command */ /* Check if CPU supports this command */
if(Registers->Leaf > MaxLeaf) if(Registers->Leaf > MaxLeaf)
@@ -55,11 +57,11 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers)
/* Execute CPUID function */ /* Execute CPUID function */
asm volatile("cpuid" asm volatile("cpuid"
: "=a" (Registers->Eax), : "=a" (Registers->Eax),
"=b" (Registers->Ebx), "=b" (Registers->Ebx),
"=c" (Registers->Ecx), "=c" (Registers->Ecx),
"=d" (Registers->Edx) "=d" (Registers->Edx)
: "a" (Registers->Leaf), : "a" (Registers->Leaf),
"c" (Registers->SubLeaf)); "c" (Registers->SubLeaf));
/* Return TRUE */ /* Return TRUE */
return TRUE; return TRUE;
@@ -183,7 +185,7 @@ HlIoPortOutByte(IN USHORT Port,
asm volatile("outb %0, %1" asm volatile("outb %0, %1"
: :
: "a"(Value), : "a"(Value),
"Nd"(Port)); "Nd"(Port));
} }
/** /**
@@ -207,7 +209,7 @@ HlIoPortOutShort(IN USHORT Port,
asm volatile("outw %0, %1" asm volatile("outw %0, %1"
: :
: "a"(Value), : "a"(Value),
"Nd"(Port)); "Nd"(Port));
} }
/** /**
@@ -231,7 +233,7 @@ HlIoPortOutLong(IN USHORT Port,
asm volatile("outl %0, %1" asm volatile("outl %0, %1"
: :
: "a"(Value), : "a"(Value),
"Nd"(Port)); "Nd"(Port));
} }
/** /**
@@ -419,5 +421,5 @@ HlWriteModelSpecificRegister(IN ULONG Register,
asm volatile("wrmsr" asm volatile("wrmsr"
: :
: "c" (Register), : "c" (Register),
"A" (Value)); "A" (Value));
} }