forked from xt-sys/exectos
.github
bootdata
sdk
cmake
ovmf
xtbk
xtdk
amd64
i686
README.md
blfuncs.h
bltypes.h
exfuncs.h
extypes.h
hlfuncs.h
hltypes.h
iotypes.h
kefuncs.h
ketypes.h
ldrtypes.h
potypes.h
pstypes.h
rtlfuncs.h
rtltypes.h
xtbase.h
xtblapi.h
xtdebug.h
xtdefs.h
xtfw.h
xtglyph.h
xtguid.h
xtimage.h
xtkmapi.h
xtstatus.h
xtstruct.h
xttarget.h
xttypes.h
xtuefi.h
xtldr
xtoskrnl
.clangd
.gitignore
CMakeLists.txt
CONTRIBUTING.md
COPYING.md
ExectOS.code-workspace
IDEAS.md
KNOWN_ISSUES.md
README.md
configure.sh
148 lines
4.7 KiB
C
148 lines
4.7 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: sdk/xtdk/iotypes.h
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* DESCRIPTION: I/O related type definitions
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#ifndef __XTDK_IOTYPES_H
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#define __XTDK_IOTYPES_H
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#include <xttypes.h>
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/* Number of PCI base address registers */
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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#define PCI_TYPE2_ADDRESSES 5
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/* PCI maximum number of devices */
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#define PCI_MAX_BRIDGE_NUMBER 255
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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/* Invalid PCI vendor ID */
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#define PCI_INVALID_VENDORID 0xFFFF
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/* PCI common config header types */
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#define PCI_DEVICE_TYPE 0x00
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#define PCI_BRIDGE_TYPE 0x01
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#define PCI_CARDBUS_BRIDGE_TYPE 0x02
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#define PCI_MULTIFUNCTION 0x80
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/* PCI common config commands */
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#define PCI_ENABLE_IO_SPACE 0x0001
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#define PCI_ENABLE_MEMORY_SPACE 0x0002
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#define PCI_ENABLE_BUS_MASTER 0x0004
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#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
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#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
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#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
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#define PCI_ENABLE_PARITY 0x0040
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#define PCI_ENABLE_WAIT_CYCLE 0x0080
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#define PCI_ENABLE_SERR 0x0100
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#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200
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#define PCI_DISABLE_LEVEL_INTERRUPT 0x0400
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/* PCI common config statuses */
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#define PCI_STATUS_INTERRUPT_PENDING 0x0008
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#define PCI_STATUS_CAPABILITIES_LIST 0x0010
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#define PCI_STATUS_66MHZ_CAPABLE 0x0020
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#define PCI_STATUS_UDF_SUPPORTED 0x0040
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#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080
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#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
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#define PCI_STATUS_DEVSEL 0x0600
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#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
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#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
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#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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/* PCI and PCI-E common header structure */
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typedef struct _PCI_COMMON_HEADER
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{
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USHORT VendorId;
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USHORT DeviceId;
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USHORT Command;
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USHORT Status;
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UCHAR RevisionId;
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UCHAR ProgIf;
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UCHAR SubClass;
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UCHAR BaseClass;
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UCHAR CacheLineSize;
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UCHAR LatencyTimer;
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UCHAR HeaderType;
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UCHAR BIST;
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union
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{
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struct _PCI_TYPE0_HEADER
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{
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ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
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ULONG CIS;
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USHORT SubVendorId;
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USHORT SubSystemId;
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ULONG ROMBaseAddress;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved1[3];
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ULONG Reserved2;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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UCHAR MinimumGrant;
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UCHAR MaximumLatency;
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} type0;
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struct _PCI_TYPE1_HEADER
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{
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ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatency;
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UCHAR IOBase;
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UCHAR IOLimit;
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USHORT SecondaryStatus;
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USHORT MemoryBase;
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USHORT MemoryLimit;
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USHORT PrefetchBase;
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USHORT PrefetchLimit;
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ULONG PrefetchBaseUpper32;
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ULONG PrefetchLimitUpper32;
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USHORT IOBaseUpper16;
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USHORT IOLimitUpper16;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved1[3];
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ULONG ROMBaseAddress;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type1;
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struct _PCI_TYPE2_HEADER
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{
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ULONG SocketRegistersBaseAddress;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved;
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USHORT SecondaryStatus;
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatency;
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struct
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{
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ULONG Base;
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ULONG Limit;
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} Range[PCI_TYPE2_ADDRESSES - 1];
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type2;
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} u;
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} PCI_COMMON_HEADER, *PPCI_COMMON_HEADER;
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/* PCI and PCI-E common config structure */
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typedef struct _PCI_COMMON_CONFIG
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{
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PCI_COMMON_HEADER PciHeader;
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UCHAR DeviceSpecific[192];
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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#endif /* __XTDK_IOTYPES_H */
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