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Cleanup APIC related headers

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This commit is contained in:
Rafal Kupiec 2024-06-06 21:50:20 +02:00
parent 4212453cf5
commit 92e861ebae
Signed by: belliash
GPG Key ID: 4E829243E0CFE6B4
5 changed files with 256 additions and 150 deletions
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47
sdk/xtdk/amd64/hltypes.h
View File

@ -56,6 +56,9 @@
#define APIC_TGM_EDGE 0 #define APIC_TGM_EDGE 0
#define APIC_TGM_LEVEL 1 #define APIC_TGM_LEVEL 1
/* Maximum number of I/O APICs */
#define APIC_MAX_IOAPICS 64
/* 8259/ISP PIC ports definitions */ /* 8259/ISP PIC ports definitions */
#define PIC1_CONTROL_PORT 0x20 #define PIC1_CONTROL_PORT 0x20
#define PIC1_DATA_PORT 0x21 #define PIC1_DATA_PORT 0x21
@ -71,6 +74,50 @@
/* Initial stall factor */ /* Initial stall factor */
#define INITIAL_STALL_FACTOR 100 #define INITIAL_STALL_FACTOR 100
/* APIC Register Address Map */
typedef enum _APIC_REGISTER
{
APIC_ID = 0x02, /* APIC ID Register */
APIC_VER = 0x03, /* APIC Version Register */
APIC_TPR = 0x08, /* Task Priority Register */
APIC_APR = 0x09, /* Arbitration Priority Register */
APIC_PPR = 0x0A, /* Processor Priority Register (R) */
APIC_EOI = 0x0B, /* EOI Register */
APIC_RRR = 0x0C, /* Remote Read Register */
APIC_LDR = 0x0D, /* Logical Destination Register */
APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
APIC_ISR = 0x10, /* Interrupt Service Register*/
APIC_TMR = 0x18, /* Trigger Mode Register */
APIC_IRR = 0x20, /* Interrupt Request Register */
APIC_ESR = 0x28, /* Error Status Register */
APIC_ICR0 = 0x30, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
APIC_LINT0 = 0x35, /* LINT0 Local Vector Table */
APIC_LINT1 = 0x36, /* LINT1 Local Vector Table */
APIC_ERRLVTR = 0x37, /* Error Local Vector Table */
APIC_TICR = 0x38, /* Initial Count Register for Timer */
APIC_TCCR = 0x39, /* Current Count Register for Timer */
APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */
APIC_EAFR = 0x40, /* extended APIC Feature register */
APIC_EACR = 0x41, /* Extended APIC Control Register */
APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */
APIC_EXT0LVTR = 0x50, /* Extended Interrupt 0 Local Vector Table */
APIC_EXT1LVTR = 0x51, /* Extended Interrupt 1 Local Vector Table */
APIC_EXT2LVTR = 0x52, /* Extended Interrupt 2 Local Vector Table */
APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
} APIC_REGISTER, *PAPIC_REGISTER;
/* APIC mode list */
typedef enum _APIC_MODE
{
APIC_MODE_COMPAT,
APIC_MODE_X2APIC
} APIC_MODE, *PAPIC_MODE;
/* APIC destination short-hand enumeration list */ /* APIC destination short-hand enumeration list */
typedef enum _APIC_DSH typedef enum _APIC_DSH
{ {

100
sdk/xtdk/hltypes.h
View File

@ -12,6 +12,7 @@
#include <xtbase.h> #include <xtbase.h>
#include <xtdefs.h> #include <xtdefs.h>
#include <xttypes.h> #include <xttypes.h>
#include ARCH_HEADER(hltypes.h)
/* ACPI Root System Description Pointer (RSDP) signature */ /* ACPI Root System Description Pointer (RSDP) signature */
@ -66,6 +67,21 @@
#define ACPI_FADT_TIMER_32BIT 0x80000000 #define ACPI_FADT_TIMER_32BIT 0x80000000
#define ACPI_FADT_TIMER_24BIT 0x00800000 #define ACPI_FADT_TIMER_24BIT 0x00800000
/* ACPI MADT subtable type definitions */
#define ACPI_MADT_LOCAL_APIC 0
#define ACPI_MADT_IOAPIC 1
#define ACPI_MADT_INT_OVERRIDE 2
#define ACPI_MADT_NMI_SOURCE 3
#define ACPI_MADT_LOCAL_NMI_SOURCE 4
#define ACPI_MADT_ADDRESS_EXTENSION 5
#define ACPI_MADT_IO_SAPIC 6
#define ACPI_MADT_LOCAL_SAPIC 7
#define ACPI_MADT_PLATFORM_INTERRUPT_SOURCE 8
/* ACPI MADT Processor Local APIC Flags */
#define ACPI_MADT_PLACE_ENABLED 0 /* Processor Local APIC CPU Enabled */
#define ACPI_MADT_PLAOC_ENABLED 1 /* Processor Local APIC Online Capable */
/* Default serial port settings */ /* Default serial port settings */
#define COMPORT_CLOCK_RATE 0x1C200 #define COMPORT_CLOCK_RATE 0x1C200
#define COMPORT_WAIT_TIMEOUT 204800 #define COMPORT_WAIT_TIMEOUT 204800
@ -144,50 +160,6 @@
#define COMPORT_REG_MSR 0x06 /* Modem Status Register */ #define COMPORT_REG_MSR 0x06 /* Modem Status Register */
#define COMPORT_REG_SR 0x07 /* Scratch Register */ #define COMPORT_REG_SR 0x07 /* Scratch Register */
/* APIC Register Address Map */
typedef enum _APIC_REGISTER
{
APIC_ID = 0x02, /* APIC ID Register */
APIC_VER = 0x03, /* APIC Version Register */
APIC_TPR = 0x08, /* Task Priority Register */
APIC_APR = 0x09, /* Arbitration Priority Register */
APIC_PPR = 0x0A, /* Processor Priority Register (R) */
APIC_EOI = 0x0B, /* EOI Register */
APIC_RRR = 0x0C, /* Remote Read Register */
APIC_LDR = 0x0D, /* Logical Destination Register */
APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
APIC_ISR = 0x10, /* Interrupt Service Register*/
APIC_TMR = 0x18, /* Trigger Mode Register */
APIC_IRR = 0x20, /* Interrupt Request Register */
APIC_ESR = 0x28, /* Error Status Register */
APIC_ICR0 = 0x30, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
APIC_LINT0 = 0x35, /* LINT0 Local Vector Table */
APIC_LINT1 = 0x36, /* LINT1 Local Vector Table */
APIC_ERRLVTR = 0x37, /* Error Local Vector Table */
APIC_TICR = 0x38, /* Initial Count Register for Timer */
APIC_TCCR = 0x39, /* Current Count Register for Timer */
APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */
APIC_EAFR = 0x40, /* extended APIC Feature register */
APIC_EACR = 0x41, /* Extended APIC Control Register */
APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */
APIC_EXT0LVTR = 0x50, /* Extended Interrupt 0 Local Vector Table */
APIC_EXT1LVTR = 0x51, /* Extended Interrupt 1 Local Vector Table */
APIC_EXT2LVTR = 0x52, /* Extended Interrupt 2 Local Vector Table */
APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
} APIC_REGISTER, *PAPIC_REGISTER;
/* APIC mode list */
typedef enum _HAL_APIC_MODE
{
APIC_MODE_COMPAT,
APIC_MODE_X2APIC
} HAL_APIC_MODE, *PHAL_APIC_MODE;
/* Generic Address structure */ /* Generic Address structure */
typedef struct _GENERIC_ADDRESS typedef struct _GENERIC_ADDRESS
{ {
@ -212,6 +184,13 @@ typedef struct _ACPI_DESCRIPTION_HEADER
ULONG CreatorRev; ULONG CreatorRev;
} ACPI_DESCRIPTION_HEADER, *PACPI_DESCRIPTION_HEADER; } ACPI_DESCRIPTION_HEADER, *PACPI_DESCRIPTION_HEADER;
/* Each ACPI subtable description header structure */
typedef struct _ACPI_SUBTABLE_HEADER
{
UCHAR Type;
UCHAR Length;
} ACPI_SUBTABLE_HEADER, *PACPI_SUBTABLE_HEADER;
/* ACPI cache list structure */ /* ACPI cache list structure */
typedef struct _ACPI_CACHE_LIST typedef struct _ACPI_CACHE_LIST
{ {
@ -307,6 +286,39 @@ typedef struct _ACPI_FADT
GENERIC_ADDRESS SleepStatusReg; GENERIC_ADDRESS SleepStatusReg;
} ACPI_FADT, *PACPI_FADT; } ACPI_FADT, *PACPI_FADT;
/* ACPI Multiple APIC Description Table (MADT) structure */
typedef struct _ACPI_MADT
{
ACPI_DESCRIPTION_HEADER Header;
ULONG LocalApicAddress;
ULONG Flags;
ULONG ApicTables[];
} ACPI_MADT, *PACPI_MADT;
typedef struct _ACPI_MADT_TABLE_LOCAL_APIC
{
ACPI_SUBTABLE_HEADER Header;
UCHAR ProcessorId;
UCHAR Id;
ULONG LapicFlags;
} ACPI_MADT_TABLE_LOCAL_APIC, *PACPI_MADT_TABLE_LOCAL_APIC;
/* ACPI System Information */
typedef struct _ACPI_SYSTEM_INFO
{
ULONG CpuCount;
ULONG RunningCpus;
ULONG BusCount;
ULONG IoApicCount;
ULONG IntiCount;
ULONG LintiCount;
ULONG ImcrPresent;
ULONG ApicBase;
ULONG IoApicPhysicalBase[APIC_MAX_IOAPICS];
PULONG IoApicVirtualBase[APIC_MAX_IOAPICS];
ULONG IoApicIntiBase[APIC_MAX_IOAPICS];
} ACPI_SYSTEM_INFO, *PACPI_SYSTEM_INFO;
/* ACPI Timer information structure */ /* ACPI Timer information structure */
typedef struct _ACPI_TIMER_INFO typedef struct _ACPI_TIMER_INFO
{ {

47
sdk/xtdk/i686/hltypes.h
View File

@ -61,6 +61,9 @@
#define APIC_TGM_EDGE 0 #define APIC_TGM_EDGE 0
#define APIC_TGM_LEVEL 1 #define APIC_TGM_LEVEL 1
/* Maximum number of I/O APICs */
#define APIC_MAX_IOAPICS 64
/* 8259/ISP PIC ports definitions */ /* 8259/ISP PIC ports definitions */
#define PIC1_CONTROL_PORT 0x20 #define PIC1_CONTROL_PORT 0x20
#define PIC1_DATA_PORT 0x21 #define PIC1_DATA_PORT 0x21
@ -78,6 +81,50 @@
/* Initial stall factor */ /* Initial stall factor */
#define INITIAL_STALL_FACTOR 100 #define INITIAL_STALL_FACTOR 100
/* APIC Register Address Map */
typedef enum _APIC_REGISTER
{
APIC_ID = 0x02, /* APIC ID Register */
APIC_VER = 0x03, /* APIC Version Register */
APIC_TPR = 0x08, /* Task Priority Register */
APIC_APR = 0x09, /* Arbitration Priority Register */
APIC_PPR = 0x0A, /* Processor Priority Register (R) */
APIC_EOI = 0x0B, /* EOI Register */
APIC_RRR = 0x0C, /* Remote Read Register */
APIC_LDR = 0x0D, /* Logical Destination Register */
APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
APIC_ISR = 0x10, /* Interrupt Service Register*/
APIC_TMR = 0x18, /* Trigger Mode Register */
APIC_IRR = 0x20, /* Interrupt Request Register */
APIC_ESR = 0x28, /* Error Status Register */
APIC_ICR0 = 0x30, /* Interrupt Command Register */
APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
APIC_LINT0 = 0x35, /* LINT0 Local Vector Table */
APIC_LINT1 = 0x36, /* LINT1 Local Vector Table */
APIC_ERRLVTR = 0x37, /* Error Local Vector Table */
APIC_TICR = 0x38, /* Initial Count Register for Timer */
APIC_TCCR = 0x39, /* Current Count Register for Timer */
APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */
APIC_EAFR = 0x40, /* extended APIC Feature register */
APIC_EACR = 0x41, /* Extended APIC Control Register */
APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */
APIC_EXT0LVTR = 0x50, /* Extended Interrupt 0 Local Vector Table */
APIC_EXT1LVTR = 0x51, /* Extended Interrupt 1 Local Vector Table */
APIC_EXT2LVTR = 0x52, /* Extended Interrupt 2 Local Vector Table */
APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
} APIC_REGISTER, *PAPIC_REGISTER;
/* APIC mode list */
typedef enum _APIC_MODE
{
APIC_MODE_COMPAT,
APIC_MODE_X2APIC
} APIC_MODE, *PAPIC_MODE;
/* APIC destination short-hand enumeration list */ /* APIC destination short-hand enumeration list */
typedef enum _APIC_DSH typedef enum _APIC_DSH
{ {

2
xtoskrnl/hl/globals.c
View File

@ -22,7 +22,7 @@ ACPI_TIMER_INFO HlpAcpiTimerInfo;
KAFFINITY HlpActiveProcessors; KAFFINITY HlpActiveProcessors;
/* APIC mode */ /* APIC mode */
HAL_APIC_MODE HlpApicMode; APIC_MODE HlpApicMode;
/* FrameBuffer information */ /* FrameBuffer information */
HAL_FRAMEBUFFER_DATA HlpFrameBufferData; HAL_FRAMEBUFFER_DATA HlpFrameBufferData;

2
xtoskrnl/includes/globals.h
View File

@ -25,7 +25,7 @@ EXTERN ACPI_TIMER_INFO HlpAcpiTimerInfo;
EXTERN KAFFINITY HlpActiveProcessors; EXTERN KAFFINITY HlpActiveProcessors;
/* APIC mode */ /* APIC mode */
EXTERN HAL_APIC_MODE HlpApicMode; EXTERN APIC_MODE HlpApicMode;
/* FrameBuffer information */ /* FrameBuffer information */
EXTERN HAL_FRAMEBUFFER_DATA HlpFrameBufferData; EXTERN HAL_FRAMEBUFFER_DATA HlpFrameBufferData;