From 9c449bed43d47c99c0dab798bfcb27fc6ae9d4df Mon Sep 17 00:00:00 2001
From: Aiken Harris <harraiken91@gmail.com>
Date: Fri, 27 Mar 2026 19:16:16 +0100
Subject: [PATCH] Initialize IDT with specific trap handlers for each vector

---
 xtoskrnl/ar/amd64/archsup.S           |  9 +++++++++
 xtoskrnl/ar/amd64/procsup.cc          |  2 +-
 xtoskrnl/ar/i686/archsup.S            | 11 ++++++++++-
 xtoskrnl/ar/i686/procsup.cc           |  2 +-
 xtoskrnl/includes/ar/amd64/procsup.hh |  3 +++
 xtoskrnl/includes/ar/i686/procsup.hh  |  3 +++
 6 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/xtoskrnl/ar/amd64/archsup.S b/xtoskrnl/ar/amd64/archsup.S
index 481cd530..674f745a 100644
--- a/xtoskrnl/ar/amd64/archsup.S
+++ b/xtoskrnl/ar/amd64/archsup.S
@@ -187,3 +187,12 @@ KernelModeReturn$\Vector:
         ArCreateTrapHandler 0x\i\j
     .endr
 .endr
+
+/* Define array of pointers to the trap handlers */
+.global ArTrapEntry
+ArTrapEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .quad ArTrap0x\i\j
+    .endr
+.endr
diff --git a/xtoskrnl/ar/amd64/procsup.cc b/xtoskrnl/ar/amd64/procsup.cc
index 29720e01..d20d3a66 100644
--- a/xtoskrnl/ar/amd64/procsup.cc
+++ b/xtoskrnl/ar/amd64/procsup.cc
@@ -249,7 +249,7 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
diff --git a/xtoskrnl/ar/i686/archsup.S b/xtoskrnl/ar/i686/archsup.S
index 4e73bc1a..d5e20fe2 100644
--- a/xtoskrnl/ar/i686/archsup.S
+++ b/xtoskrnl/ar/i686/archsup.S
@@ -82,7 +82,7 @@ _ArTrap\Vector:
     jmp UserMode$\Vector
 
 KernelMode$\Vector:
-    /* Save kernel stack pointer (SS:ESP) as CPU did not push them */
+    /* Save kernel stack pointer (SS:ESP) */
     movl %ss, %eax
     mov %eax, TrapSegSs(%ebp)
     lea TrapEsp(%ebp), %eax
@@ -133,3 +133,12 @@ KernelModeReturn$\Vector:
         ArCreateTrapHandler 0x\i\j
     .endr
 .endr
+
+/* Define array of pointers to the trap handlers */
+.global ArTrapEntry
+ArTrapEntry:
+.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+    .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
+        .long ArTrap0x\i\j
+    .endr
+.endr
diff --git a/xtoskrnl/ar/i686/procsup.cc b/xtoskrnl/ar/i686/procsup.cc
index 35f645e9..b8b8da27 100644
--- a/xtoskrnl/ar/i686/procsup.cc
+++ b/xtoskrnl/ar/i686/procsup.cc
@@ -242,7 +242,7 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock)
     for(Vector = 0; Vector < IDT_ENTRIES; Vector++)
     {
         /* Set the IDT to handle unexpected interrupts */
-        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
+        SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE);
     }
 
     /* Setup IDT handlers for known interrupts and traps */
diff --git a/xtoskrnl/includes/ar/amd64/procsup.hh b/xtoskrnl/includes/ar/amd64/procsup.hh
index 4cad2470..d663596e 100644
--- a/xtoskrnl/includes/ar/amd64/procsup.hh
+++ b/xtoskrnl/includes/ar/amd64/procsup.hh
@@ -12,6 +12,9 @@
 #include <xtos.hh>
 
 
+/* External array of pointers to the trap handlers */
+XTCLINK ULONG_PTR ArTrapEntry[256];
+
 /* Architecture-specific Library */
 namespace AR
 {
diff --git a/xtoskrnl/includes/ar/i686/procsup.hh b/xtoskrnl/includes/ar/i686/procsup.hh
index 2b4931f2..de4de606 100644
--- a/xtoskrnl/includes/ar/i686/procsup.hh
+++ b/xtoskrnl/includes/ar/i686/procsup.hh
@@ -12,6 +12,9 @@
 #include <xtos.hh>
 
 
+/* External array of pointers to the trap handlers */
+XTCLINK ULONG_PTR ArTrapEntry[256];
+
 /* Architecture-specific Library */
 namespace AR
 {