diff --git a/xtoskrnl/ar/amd64/cpufunc.c b/xtoskrnl/ar/amd64/cpufunc.c
index 8104b31e..d1b21d54 100644
--- a/xtoskrnl/ar/amd64/cpufunc.c
+++ b/xtoskrnl/ar/amd64/cpufunc.c
@@ -271,6 +271,23 @@ ArLoadTaskRegister(USHORT Source)
                  : "rm" (Source));
 }
 
+/**
+ * Orders memory accesses as seen by other processors.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArMemoryBarrier()
+{
+    LONG Barrier;
+    asm volatile("lock; orl $0, %0;"
+                 :
+                 : "m"(Barrier));
+}
+
 /**
  * Reads the specified CPU control register and returns its value.
  *
@@ -485,6 +502,23 @@ ArReadTimeStampCounter()
     return ((ULONGLONG)High << 32) | Low;
 }
 
+/**
+ * Orders memory accesses as seen by other processors, without fence.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArReadWriteBarrier()
+{
+    asm volatile(""
+                 :
+                 :
+                 : "memory");
+}
+
 /**
  * Instructs the processor to set the interrupt flag.
  *
diff --git a/xtoskrnl/ar/i686/cpufunc.c b/xtoskrnl/ar/i686/cpufunc.c
index d63a89c2..a3ae24f6 100644
--- a/xtoskrnl/ar/i686/cpufunc.c
+++ b/xtoskrnl/ar/i686/cpufunc.c
@@ -252,6 +252,24 @@ ArLoadTaskRegister(USHORT Source)
                  : "rm" (Source));
 }
 
+/**
+ * Orders memory accesses as seen by other processors.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArMemoryBarrier()
+{
+   LONG Barrier;
+   asm volatile("xchg %%eax, %0"
+                :
+                : "m" (Barrier)
+                : "%eax");
+}
+
 /**
  * Reads the specified CPU control register and returns its value.
  *
@@ -454,6 +472,23 @@ ArReadTimeStampCounter()
     return Value;
 }
 
+/**
+ * Orders memory accesses as seen by other processors, without fence.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArReadWriteBarrier()
+{
+    asm volatile(""
+                 :
+                 :
+                 : "memory");
+}
+
 /**
  * Instructs the processor to set the interrupt flag.
  *
diff --git a/xtoskrnl/includes/amd64/ari.h b/xtoskrnl/includes/amd64/ari.h
index 197e51f9..9d1849e7 100644
--- a/xtoskrnl/includes/amd64/ari.h
+++ b/xtoskrnl/includes/amd64/ari.h
@@ -63,6 +63,10 @@ XTCDECL
 VOID
 ArLoadTaskRegister(USHORT Source);
 
+XTCDECL
+VOID
+ArMemoryBarrier();
+
 XTCDECL
 ULONG_PTR
 ArReadControlRegister(IN USHORT ControlRegister);
@@ -87,6 +91,10 @@ XTCDECL
 ULONGLONG
 ArReadTimeStampCounter();
 
+XTCDECL
+VOID
+ArReadWriteBarrier();
+
 XTAPI
 VOID
 ArSetGdtEntryBase(IN PKGDTENTRY Gdt,
diff --git a/xtoskrnl/includes/i686/ari.h b/xtoskrnl/includes/i686/ari.h
index 7055b3a2..69b8a495 100644
--- a/xtoskrnl/includes/i686/ari.h
+++ b/xtoskrnl/includes/i686/ari.h
@@ -59,6 +59,10 @@ XTCDECL
 VOID
 ArLoadTaskRegister(USHORT Source);
 
+XTCDECL
+VOID
+ArMemoryBarrier();
+
 XTCDECL
 ULONG_PTR
 ArReadControlRegister(IN USHORT ControlRegister);
@@ -83,6 +87,10 @@ XTCDECL
 ULONGLONG
 ArReadTimeStampCounter();
 
+XTCDECL
+VOID
+ArReadWriteBarrier();
+
 XTAPI
 VOID
 ArSetGdtEntryBase(IN PKGDTENTRY Gdt,