16 Commits

Author	SHA1	Message	Date
PerikiyoXD	363e100493	Saving processor features in the processor control block ... Fixed correct AMD Family 25 model detection Fixed procedure for saving processor vendor name (previously corrupted) Added a debugging print of the processor identification	2024-05-06 17:55:37 +02:00
Rafal Kupiec	befa211aa7	Add PFN related structures and definitions	2024-04-08 19:03:58 +02:00
Rafal Kupiec	d7b103f85d	Add forward references for PTE related structures	2024-04-03 16:03:17 +02:00
Rafal Kupiec	5acf8b4abd	Add page size enumeration list	2024-01-18 14:22:51 +01:00
belliash	10ccf67e8e	Add missing forward declarations	2023-03-14 22:50:32 +01:00
belliash	fd8eec1d86	Add EFLAGS and THREAD_ENVIRONMENT_BLOCK for amd64	2023-03-05 19:03:34 +01:00
belliash	e94cb2d3a7	Processor identification structures	2023-02-10 17:14:12 +01:00
belliash	5eaf7d63a3	Initialize Page Attribute Table	2023-02-05 00:14:34 +01:00
belliash	73fc7607cd	There is no need to specify alignment of the structure in the forward reference	2023-02-02 15:37:57 +01:00
belliash	6f068513cd	Initial processor block initialization	2023-01-30 19:07:05 +01:00
belliash	3ad3149f80	Add descriptor structure definition	2023-01-25 17:42:35 +01:00
belliash	bfc9db8b6d	Unify KGDTENTRY and KIDTENTRY between architectures as much as possible	2023-01-25 17:35:03 +01:00
belliash	ca1d7ddfe8	Basic context, frames and exceptions definitions	2023-01-07 23:36:50 +01:00
belliash	f74ba62f24	Add GDT, IDT and TSS related structures	2023-01-07 13:33:16 +01:00
belliash	324a88cc01	Implement HlCpuId() routine and corresponding structures for issueing CPUID instruction	2022-12-11 17:40:56 +01:00
belliash	35f2c67138	Basic XT structures	2022-07-29 16:31:59 +02:00