133 Commits

Author	SHA1	Message	Date
Aiken Harris	00b04f5405	Refactor IDT gate setup to use explicit DPL and type fields	2025-10-18 18:29:49 +02:00
Aiken Harris	2b49b23d41	Add trampoline support and move assembler prototypes	2025-09-19 19:07:27 +02:00
Aiken Harris	e7425de523	Drop C wrappers and switch to C++ API	2025-09-19 12:56:06 +02:00
Aiken Harris	0a0fdffc46	Clean up kernel headers	2025-09-15 22:46:57 +02:00
Aiken Harris	4592955da1	Migrate HL subsystem to C++	2025-09-13 19:15:13 +02:00
Aiken Harris	c8dc2a1407	Migrate AR subsystem to C++	2025-09-08 15:29:13 +02:00
Aiken Harris	6ee7243e04	Refactor APIC delivery mode handling and unify naming	2025-09-01 19:54:12 +02:00
Aiken Harris	d45cc5ffe5	Fix incorrect APIC delivery mode definitions	2025-09-01 19:32:29 +02:00
Aiken Harris	9f6121e9b2	Map the physical page for trampoline code	2025-08-20 20:37:55 +02:00
Aiken Harris	ebae8c655c	Expand CR4, MSR, and EFER register definitions	2025-08-19 23:59:58 +02:00
Aiken Harris	1a0bc7f65f	Update and correct CR4 bit definitions	2025-08-19 21:45:13 +02:00
Aiken Harris	1dcd3fceed	Define page map information structure for both supported architectures	2025-08-16 20:08:12 +02:00
Aiken Harris	22f81a106b	Update forward declarations for PML2/PML3 types	2025-08-16 00:33:18 +02:00
Aiken Harris	7e08dc286e	Separate types for legacy (PML2) and PAE (PML3) paging	2025-08-16 00:29:20 +02:00
Aiken Harris	560bd8b65e	Update CPUID requests	2025-08-10 16:53:45 +02:00
Aiken Harris	574582f977	Add forward declarations for CPUID feature enums	2025-08-10 16:36:32 +02:00
Aiken Harris	bb5deb10d5	Rename enumeration lists	2025-08-10 16:32:49 +02:00
Aiken Harris	a9a264252a	Add enums for CPU feature flags used in CPUID detection	2025-08-10 16:25:26 +02:00
Aiken Harris	58c2092049	Revert latest changes	2025-08-09 14:53:31 +02:00
Aiken Harris	39d8f82caf	Define MM_HARDWARE_POOL_PAGE_COUNT	2025-08-08 21:44:33 +02:00
Rafal Kupiec	7b8f4f15cc	Add APIC Logical Destination Register (LDR) shifts and correct APIC delivery mode values	2024-07-23 20:14:06 +02:00
Rafal Kupiec	906e09fd9f	Refactor COM port support, to get rid of global variables in library	2024-06-12 18:02:29 +02:00
Rafal Kupiec	86bc2042e5	Cleanup XTDK headers	2024-06-06 23:09:03 +02:00
Rafal Kupiec	92e861ebae	Cleanup APIC related headers	2024-06-06 21:50:20 +02:00
Rafal Kupiec	4212453cf5	Fix APIC initialization code	2024-06-06 16:49:08 +02:00
Rafal Kupiec	ef65bceccd	Initialize legacy PIC and mask all interrupts	2024-06-05 16:08:54 +02:00
Rafal Kupiec	6176ca38a8	Cleanup hardware allocation memory pool related code	2024-06-02 17:29:31 +02:00
Rafal Kupiec	7f8846f23d	Map memory for hardware layer on i686	2024-05-27 22:17:30 +02:00
Rafal Kupiec	70d1295919	Do not support non-PAE systems	2024-05-24 23:47:29 +02:00
Rafal Kupiec	03ba3b5583	Add missing forward references for APIC related structures	2024-05-24 23:41:27 +02:00
Rafal Kupiec	94a40501d4	Mask APIC ICR0 and disable APIC interrupts for initialization time by raising APIC TPR	2024-05-24 23:39:06 +02:00
Rafal Kupiec	b4588d5b4c	Make ExectOS only run on processors which support PAE	2024-05-24 16:30:39 +02:00
Rafal Kupiec	143803aad9	PPE needs PAE on i686	2024-05-22 23:09:30 +02:00
Rafal Kupiec	609538b9be	Implement MmpGetPdeAddress() and MmpGetPteAddress() routines for i686 architecture as well as MmpMemoryExtensionEnabled() for checking PAE/LA57 support	2024-05-22 22:47:28 +02:00
Rafal Kupiec	03727a61d3	Implement hardware layer pool memory management	2024-05-22 18:51:09 +02:00
Rafal Kupiec	efef3cb80d	Cleanup EFLAGS related definitions	2024-05-14 16:22:10 +02:00
Rafal Kupiec	38b0b2ac7d	Use correct stack when using preallocated processor structures	2024-05-08 15:57:24 +02:00
Rafal Kupiec	b65ff2a767	Implement MmAllocateProcessorStructures() routine as a temporary hack to get a buffer for AP initialization	2024-05-07 23:30:11 +02:00
Rafal Kupiec	276eb77862	Update KPROCESSOR_BLOCK structure	2024-05-07 16:20:40 +02:00
Rafal Kupiec	22693a48d3	Rework trap handling assembly code	2024-04-23 15:07:08 +02:00
Rafal Kupiec	a36c02fde8	Use common name for EFLAGS and RFLAGS, regardless the CPU architecture	2024-04-21 22:35:06 +02:00
Rafal Kupiec	92ee74b494	Rework trap handling to access registers	2024-04-19 16:52:37 +02:00
Rafal Kupiec	befa211aa7	Add PFN related structures and definitions	2024-04-08 19:03:58 +02:00
Rafal Kupiec	04e22c127e	Initial memory manager initialization code	2024-04-07 10:26:12 +02:00
Rafal Kupiec	d7b103f85d	Add forward references for PTE related structures	2024-04-03 16:03:17 +02:00
Rafal Kupiec	c6f3422c49	Update PTE related structures	2024-04-03 16:00:26 +02:00
Rafal Kupiec	4b2d8ded72	No parameters are expected, explicitly	2024-02-20 16:55:12 +01:00
Rafal Kupiec	badb16e37d	Add lock queue to processor control block	2024-02-05 19:21:19 +01:00
Rafal Kupiec	af687603d0	Add kernel stack guard pages definition	2024-02-04 19:21:42 +01:00
Rafal Kupiec	c716ad81f0	i686 supports switching to huge pages mode with 2MB or 4MB page size only	2024-01-18 14:48:43 +01:00