214 Commits

Author	SHA1	Message	Date
Aiken Harris	0d2d41dcda	Introduce page fault handling infrastructure	2025-12-29 14:53:43 +01:00
Aiken Harris	200e9132b1	Minor style fixes in MM includes	2025-12-28 23:51:34 +01:00
Aiken Harris	0880a0f344	Implement PFN database initialization and memory descriptor processing	2025-12-28 23:25:07 +01:00
Aiken Harris	4593a89a9b	Expose PFN database lookup via GetPfnEntry	2025-12-28 21:18:17 +01:00
Aiken Harris	b7c004528a	Implement tracking of available physical pages	2025-12-23 22:13:09 +01:00
Aiken Harris	5012c8dc37	Initialize system PTE pools and implement reservation routines	2025-12-23 20:16:08 +01:00
Aiken Harris	1e3917882c	Initialize system page tables and configure kernel mappings	2025-12-23 18:03:02 +01:00
Aiken Harris	288b2f8b24	Introduce page coloring support to memory manager	2025-12-23 14:27:12 +01:00
Aiken Harris	7575526f07	Fix physical page count overflow by using 64-bit type	2025-12-22 23:32:54 +01:00
Aiken Harris	e237a944cc	Extend PTE helpers with raw read and write support	2025-12-22 08:21:43 +01:00
Aiken Harris	755a167f2c	Respect architecture-specific PTE layouts and write PTEs via PML-aware helpers	2025-12-22 00:07:48 +01:00
Aiken Harris	570301bb35	Clarify page table entry offset semantics	2025-12-18 22:38:59 +01:00
Aiken Harris	b183d52806	Fix paging abstraction for PDE/PTE virtual address calculation	2025-12-18 22:26:31 +01:00
Aiken Harris	cb4d113e31	Add virtual address validation and system PTE helpers	2025-12-16 22:31:15 +01:00
Aiken Harris	00d428d8de	Architecture-specific system PTE limits	2025-12-16 20:05:51 +01:00
Aiken Harris	2265a4a522	Remove unsupported PML4/PML5 PTE interfaces	2025-12-16 14:13:55 +01:00
Aiken Harris	dc23f91110	Split PTE implementation per architecture	2025-12-16 14:08:32 +01:00
Aiken Harris	7f0ca6a948	Compute PTE count per page from entry size	2025-12-15 13:56:39 +01:00
Aiken Harris	36c273ea13	Implement early page table mapping routines	2025-12-15 13:24:02 +01:00
Aiken Harris	5cf3dfa844	Add bootstrap physical page allocator	2025-12-15 12:38:08 +01:00
Aiken Harris	070c508e42	Introduce kernel virtual memory layout	2025-12-14 15:35:24 +01:00
Aiken Harris	5224dc315f	Compute PFN database size during MM initialization	2025-12-13 22:50:27 +01:00
Aiken Harris	eae48320f3	Harden PFN initialization and expose page count	2025-12-13 21:01:13 +01:00
Aiken Harris	17b5649362	Make memory type verification helpers accessible to PFN	2025-12-13 20:50:32 +01:00
Aiken Harris	783a9eea3a	Extract PFN management into separate module	2025-12-13 20:42:48 +01:00
Aiken Harris	237f6a2974	Refactor memory manager initialization into MM::Manager	2025-12-13 20:21:08 +01:00
Aiken Harris	ee9514fd5c	Fix GetP5eAddress return type	2025-12-13 19:58:49 +01:00
Aiken Harris	63c27a149a	Add missing virtual GetPteDistance to pagemap interface	2025-12-06 00:29:51 +01:00
Aiken Harris	7694df7744	Add architecture-specific GetPteDistance	2025-12-06 00:19:24 +01:00
Aiken Harris	c710ec4688	Refactor XPA detection API	2025-12-04 23:07:59 +01:00
Aiken Harris	86aa22e5f8	Fix incorrect pointer types	2025-11-30 20:03:12 +01:00
Aiken Harris	4a7494ad3f	Split paging interface into arch-specific code	2025-11-30 19:19:32 +01:00
Aiken Harris	d4287198b0	Implement virtual address resolvers for all page map levels and add XPA status accessor	2025-11-30 18:23:51 +01:00
Aiken Harris	4265ae92d0	Add MM::PageMap::GetXpaStatus() for querying PML level	2025-11-29 23:45:00 +01:00
Aiken Harris	931586eebd	Refactor PageMap to enable architecture-specific VA translation	2025-11-29 23:37:08 +01:00
Aiken Harris	66f27e4b9a	Add GetPageFrameNumber() to PTE interfaces	2025-11-04 23:03:47 +01:00
Aiken Harris	10b8ab347a	Make MM::Paging::GetExtendedPhysicalAddressingStatus public	2025-11-04 22:51:34 +01:00
Aiken Harris	071c840ca8	Replace writable flag with AttributesMask in PTE setup	2025-11-04 17:34:49 +01:00
Aiken Harris	cb2da54956	Unify PTE pointer types across MM subsystem	2025-11-03 22:13:32 +01:00
Aiken Harris	c28c3f8344	Add input qualifiers to page map interface definitions	2025-11-03 20:04:21 +01:00
Aiken Harris	dfb0284427	Add input qualifiers to paging interface definitions	2025-11-03 16:00:46 +01:00
Aiken Harris	1150b9ecdb	Add PTE management routines	2025-10-30 22:03:25 +01:00
Aiken Harris	ffa480d69a	Implement unified PTE accessors and management helpers	2025-10-30 20:14:02 +01:00
Aiken Harris	0120ba167f	Introduce RAII helpers for runlevel transitions	2025-10-29 23:07:27 +01:00
Aiken Harris	164ff0c135	Expand spinlock queue levels	2025-10-28 08:35:34 +01:00
Aiken Harris	f538d035e2	Introduce global spinlock initialization and RAII guard classes	2025-10-27 20:48:44 +01:00
Aiken Harris	00b04f5405	Refactor IDT gate setup to use explicit DPL and type fields	2025-10-18 18:29:49 +02:00
Aiken Harris	ae4b95380a	Fix AP startup symbol name	2025-09-19 19:23:39 +02:00
Aiken Harris	2b49b23d41	Add trampoline support and move assembler prototypes	2025-09-19 19:07:27 +02:00
Aiken Harris	d0577611ca	Move asm headers	2025-09-19 13:47:18 +02:00