2 Révisions

Auteur	SHA1	Message	Date
Aiken Harris	52afd31e77	Implement Stage2 loading in VBR code	2025-10-17 20:44:57 +02:00
Aiken Harris	764fec4d75	Implement low-level CPU initialization support for i686 and AMD64 boot sectors	2025-10-17 09:05:24 +02:00