15 Commits

Author	SHA1	Message	Date
Aiken Harris	87a91bfeb1	Make XTDK headers assembly-safe	2026-04-01 16:05:34 +02:00
Aiken Harris	232b92fd7e	Implement spurious interrupt handler	2026-04-01 13:03:46 +02:00
Aiken Harris	620fc24cd2	Fix previous mode detection by reading CS from the trap frame and sanitize segment restoration	2026-03-31 20:38:21 +02:00
Aiken Harris	494b615dc2	Fix x64 ABI compliance by aligning stack and reserving shadow space	2026-03-31 20:06:25 +02:00
Aiken Harris	987b8f45d7	Unify trap handler macro name	2026-03-31 15:53:11 +02:00
Aiken Harris	32d3672a51	Generate distinct handlers for CPU traps and hardware interrupts	2026-03-27 20:42:41 +01:00
Aiken Harris	9c449bed43	Initialize IDT with specific trap handlers for each vector	2026-03-27 19:16:16 +01:00
Aiken Harris	0fed593147	Ensure SS and RSP are saved in trap frame	2026-03-15 17:32:01 +01:00
Aiken Harris	d0577611ca	Move asm headers	2025-09-19 13:47:18 +02:00
Aiken Harris	c8dc2a1407	Migrate AR subsystem to C++	2025-09-08 15:29:13 +02:00
Aiken Harris	c4a7df6f38	Extract trampoline code into a separate file	2025-08-20 20:20:35 +02:00
Aiken Harris	2468d80078	Add trampoline to enable 5-level paging	2025-08-20 00:20:10 +02:00
Rafal Kupiec	cf0d23b6fe	Correct a typo causing page fault during int handling after switching to new kernel stack	2024-05-06 16:47:12 +02:00
Rafal Kupiec	22693a48d3	Rework trap handling assembly code	2024-04-23 15:07:08 +02:00
Rafal Kupiec	92ee74b494	Rework trap handling to access registers	2024-04-19 16:52:37 +02:00