7 Commits

Author	SHA1	Message	Date
Aiken Harris	52afd31e77	Implement Stage2 loading in VBR code	2025-10-17 20:44:57 +02:00
Aiken Harris	7f06abf236	New message for unsupported CPUs	2025-10-17 09:18:49 +02:00
Aiken Harris	4f4df52d3d	Include architecture-specific code in VBR	2025-10-17 09:12:54 +02:00
Aiken Harris	fdbe157c18	Fix CHS sector-by-sector read loop	2025-10-10 19:05:23 +02:00
Aiken Harris	56a1a811b9	Fix multi-sector read using CHS mode	2025-10-10 15:10:42 +02:00
Aiken Harris	6a8a561484	Implement disk read and error handling in VBR	2025-10-07 20:09:36 +02:00
Aiken Harris	64733914f2	Add VBR stub	2025-10-05 17:24:25 +02:00