4 Commits

Include renames

Author	SHA1	Message	Date
harraiken	52afd31e77	Implement Stage2 loading in VBR code	2025-10-17 20:44:57 +02:00
harraiken	764fec4d75	Implement low-level CPU initialization support for i686 and AMD64 boot sectors	2025-10-17 09:05:24 +02:00
belliash	f152e2bac7	Move MBR boot code to common, arch-independent place	2025-09-27 14:10:13 +02:00
belliash	f81e895fe1	Add MBR boot code	2025-09-27 14:07:17 +02:00