88 Commits

Author	SHA1	Message	Date
Aiken Harris	9ea79c92a6	Refactor assembly includes and delete manual offset definitions	2026-04-02 10:50:00 +02:00
Aiken Harris	87a91bfeb1	Make XTDK headers assembly-safe	2026-04-01 16:05:34 +02:00
Aiken Harris	232b92fd7e	Implement spurious interrupt handler	2026-04-01 13:03:46 +02:00
Aiken Harris	d88f9f0a15	Remove erroneous swapgs and implement proper segment setting	2026-04-01 11:18:28 +02:00
Aiken Harris	d00577ac8d	Fix previous mode detection by reading CS from the trap frame	2026-03-31 23:10:45 +02:00
Aiken Harris	d834b7e0c8	Correct kernel stack base calculation for downward growing stacks	2026-03-31 18:59:59 +02:00
Aiken Harris	121f461491	Refactor trap handling to support task gates	2026-03-31 12:58:46 +02:00
Aiken Harris	f4b189adef	Fix incorrect descriptor type used for NMI TSS	2026-03-30 22:20:09 +02:00
Aiken Harris	40c4860548	Refine LDT setup and restore critical TSS fields for hardware exceptions	2026-03-30 20:29:43 +02:00
Aiken Harris	d2a7ae46ac	Fix hardware task gate configuration	2026-03-30 20:16:44 +02:00
Aiken Harris	8a02a5aca3	Explicitly load GS and SS registers during segment initialization	2026-03-30 18:43:52 +02:00
Aiken Harris	96df5a80b8	Set CR3 field in TSS to ensure correct page table context on task switches	2026-03-30 14:56:41 +02:00
Aiken Harris	489ef8a514	Update IDT gate types for i686 exception handlers	2026-03-30 13:31:20 +02:00
Aiken Harris	8c6c63465f	Use dedicated NMI stack on i686	2026-03-30 11:43:09 +02:00
Aiken Harris	32d3672a51	Generate distinct handlers for CPU traps and hardware interrupts	2026-03-27 20:42:41 +01:00
Aiken Harris	0c17337388	Fix symbol naming convention for i686 trap handlers	2026-03-27 19:23:37 +01:00
Aiken Harris	9c449bed43	Initialize IDT with specific trap handlers for each vector	2026-03-27 19:16:16 +01:00
Aiken Harris	6cdb66cbb3	Ensure SS and ESP are saved in trap frame	2026-03-15 00:33:09 +01:00
Aiken Harris	00b04f5405	Refactor IDT gate setup to use explicit DPL and type fields	2025-10-18 18:29:49 +02:00
Aiken Harris	332e57f305	Add register dump to trap handler	2025-09-25 08:28:02 +02:00
Aiken Harris	ae4b95380a	Fix AP startup symbol name	2025-09-19 19:23:39 +02:00
Aiken Harris	2b49b23d41	Add trampoline support and move assembler prototypes	2025-09-19 19:07:27 +02:00
Aiken Harris	d0577611ca	Move asm headers	2025-09-19 13:47:18 +02:00
Aiken Harris	4c380bae1c	Fix build by replacing leftover Ar calls	2025-09-19 13:29:15 +02:00
Aiken Harris	1b0468f742	Fix build by replacing leftover Ar calls	2025-09-19 13:26:26 +02:00
Aiken Harris	e7425de523	Drop C wrappers and switch to C++ API	2025-09-19 12:56:06 +02:00
Aiken Harris	fabf3a3a5e	Replace all occurrences of NULL with NULLPTR for unified C and C++ null pointer handling	2025-09-16 15:59:56 +02:00
Aiken Harris	307ec1794c	Clean up after migration to C++	2025-09-16 14:20:20 +02:00
Aiken Harris	f4561c1f4f	Remove leftover old headers and fix missed spots	2025-09-16 08:46:53 +02:00
Aiken Harris	ee97388981	Switch i686 processor structures setup to use class data	2025-09-15 22:50:52 +02:00
Aiken Harris	4592955da1	Migrate HL subsystem to C++	2025-09-13 19:15:13 +02:00
Aiken Harris	3a11d536d5	Refactor AR subsystem	2025-09-11 20:23:51 +02:00
Aiken Harris	4947f788d5	Migrate KE subsystem to C++	2025-09-09 23:20:50 +02:00
Aiken Harris	c8dc2a1407	Migrate AR subsystem to C++	2025-09-08 15:29:13 +02:00
Aiken Harris	c4a7df6f38	Extract trampoline code into a separate file	2025-08-20 20:20:35 +02:00
Aiken Harris	e8771dfc5b	Use __asm__ to comply with disabled GNU extensions	2025-08-15 00:32:56 +02:00
Aiken Harris	d806c8e1f2	Resolve compilation errors due to renamed CPUID requests	2025-08-10 17:12:06 +02:00
Rafal Kupiec	740df726e9	Implement ArInterruptsEnabled() routine	2024-05-17 23:19:25 +02:00
Rafal Kupiec	5591e1b377	Fix ArGetCpuFlags() routine	2024-05-17 23:16:16 +02:00
Rafal Kupiec	9f1a4f0ced	Compose the AMD family and model IDs according to the AMD CPUID manual, section 2	2024-05-14 19:39:07 +02:00
Rafal Kupiec	2a8cc7397e	Implement ArGetCpuFlags() routine	2024-05-14 16:26:02 +02:00
Rafal Kupiec	38b0b2ac7d	Use correct stack when using preallocated processor structures	2024-05-08 15:57:24 +02:00
Rafal Kupiec	3c3a756771	Allow to initialize CPU with allocated processor structures	2024-05-08 00:02:47 +02:00
Rafal Kupiec	2c384d780f	Fix storing CPU vendor name in PRCB	2024-05-06 20:01:19 +02:00
Rafal Kupiec	22693a48d3	Rework trap handling assembly code	2024-04-23 15:07:08 +02:00
Rafal Kupiec	9f2279f28f	Use common way of setting initial runlevel across architectures	2024-04-19 23:56:33 +02:00
Rafal Kupiec	92ee74b494	Rework trap handling to access registers	2024-04-19 16:52:37 +02:00
Rafal Kupiec	8aa33874ff	Initialize CS segment on i686 architecture	2024-04-17 18:27:57 +02:00
Rafal Kupiec	b31aa82872	Fix loading CS segment for i686 architecture	2024-04-17 16:46:03 +02:00
Rafal Kupiec	4b2d8ded72	No parameters are expected, explicitly	2024-02-20 16:55:12 +01:00