86 Commits

Author	SHA1	Message	Date
Aiken Harris	a0d5ee17c2	Replace trap dispatch wrappers with direct symbol mapping	2026-04-07 12:56:33 +02:00
Rafal Kupiec	9935d2d26b	Update CPU identification code	2026-04-06 21:17:58 +02:00
Aiken Harris	09516835d0	Consolidate boot and architecture support code into a single assembly file	2026-04-02 15:08:12 +02:00
Aiken Harris	9ea79c92a6	Refactor assembly includes and delete manual offset definitions	2026-04-02 10:50:00 +02:00
Aiken Harris	87a91bfeb1	Make XTDK headers assembly-safe	2026-04-01 16:05:34 +02:00
Aiken Harris	232b92fd7e	Implement spurious interrupt handler	2026-04-01 13:03:46 +02:00
Aiken Harris	154b2062ba	Unify GDT selector naming convention	2026-04-01 11:02:05 +02:00
Aiken Harris	620fc24cd2	Fix previous mode detection by reading CS from the trap frame and sanitize segment restoration	2026-03-31 20:38:21 +02:00
Aiken Harris	494b615dc2	Fix x64 ABI compliance by aligning stack and reserving shadow space	2026-03-31 20:06:25 +02:00
Aiken Harris	d834b7e0c8	Correct kernel stack base calculation for downward growing stacks	2026-03-31 18:59:59 +02:00
Aiken Harris	987b8f45d7	Unify trap handler macro name	2026-03-31 15:53:11 +02:00
Aiken Harris	a608b26fde	Implement NMI stack handling via IST	2026-03-28 20:49:18 +01:00
Aiken Harris	32d3672a51	Generate distinct handlers for CPU traps and hardware interrupts	2026-03-27 20:42:41 +01:00
Aiken Harris	9c449bed43	Initialize IDT with specific trap handlers for each vector	2026-03-27 19:16:16 +01:00
Aiken Harris	0fed593147	Ensure SS and RSP are saved in trap frame	2026-03-15 17:32:01 +01:00
Aiken Harris	00b04f5405	Refactor IDT gate setup to use explicit DPL and type fields	2025-10-18 18:29:49 +02:00
Aiken Harris	332e57f305	Add register dump to trap handler	2025-09-25 08:28:02 +02:00
Aiken Harris	2b49b23d41	Add trampoline support and move assembler prototypes	2025-09-19 19:07:27 +02:00
Aiken Harris	d0577611ca	Move asm headers	2025-09-19 13:47:18 +02:00
Aiken Harris	e7425de523	Drop C wrappers and switch to C++ API	2025-09-19 12:56:06 +02:00
Aiken Harris	fabf3a3a5e	Replace all occurrences of NULL with NULLPTR for unified C and C++ null pointer handling	2025-09-16 15:59:56 +02:00
Aiken Harris	307ec1794c	Clean up after migration to C++	2025-09-16 14:20:20 +02:00
Aiken Harris	f4561c1f4f	Remove leftover old headers and fix missed spots	2025-09-16 08:46:53 +02:00
Aiken Harris	4592955da1	Migrate HL subsystem to C++	2025-09-13 19:15:13 +02:00
Aiken Harris	3a11d536d5	Refactor AR subsystem	2025-09-11 20:23:51 +02:00
Aiken Harris	4947f788d5	Migrate KE subsystem to C++	2025-09-09 23:20:50 +02:00
Aiken Harris	3f5f57ef12	Remove leftover test code	2025-09-08 15:44:12 +02:00
Aiken Harris	c8dc2a1407	Migrate AR subsystem to C++	2025-09-08 15:29:13 +02:00
Aiken Harris	c4a7df6f38	Extract trampoline code into a separate file	2025-08-20 20:20:35 +02:00
Aiken Harris	2468d80078	Add trampoline to enable 5-level paging	2025-08-20 00:20:10 +02:00
Aiken Harris	e8771dfc5b	Use __asm__ to comply with disabled GNU extensions	2025-08-15 00:32:56 +02:00
Aiken Harris	2ea306097d	Resolve compilation errors due to renamed CPUID requests	2025-08-10 17:10:01 +02:00
Aiken Harris	ff41b0d4f7	Fix incorrect TSS descriptor limit according to architecture specification	2025-07-28 18:25:47 +02:00
Rafal Kupiec	740df726e9	Implement ArInterruptsEnabled() routine	2024-05-17 23:19:25 +02:00
Rafal Kupiec	5591e1b377	Fix ArGetCpuFlags() routine	2024-05-17 23:16:16 +02:00
Rafal Kupiec	9f1a4f0ced	Compose the AMD family and model IDs according to the AMD CPUID manual, section 2	2024-05-14 19:39:07 +02:00
Rafal Kupiec	2a8cc7397e	Implement ArGetCpuFlags() routine	2024-05-14 16:26:02 +02:00
Rafal Kupiec	38b0b2ac7d	Use correct stack when using preallocated processor structures	2024-05-08 15:57:24 +02:00
Rafal Kupiec	3c3a756771	Allow to initialize CPU with allocated processor structures	2024-05-08 00:02:47 +02:00
Rafal Kupiec	2c384d780f	Fix storing CPU vendor name in PRCB	2024-05-06 20:01:19 +02:00
Rafal Kupiec	cf0d23b6fe	Correct a typo causing page fault during int handling after switching to new kernel stack	2024-05-06 16:47:12 +02:00
Rafal Kupiec	22693a48d3	Rework trap handling assembly code	2024-04-23 15:07:08 +02:00
Rafal Kupiec	3aa0413756	Use common routine to set runlevel	2024-04-19 23:52:21 +02:00
Rafal Kupiec	28c89986fb	Tweaks to AMD64 architecture support	2024-04-19 23:37:39 +02:00
Rafal Kupiec	92ee74b494	Rework trap handling to access registers	2024-04-19 16:52:37 +02:00
Rafal Kupiec	cf408519ad	Initialize AMD64 segments properly	2024-04-17 20:02:27 +02:00
Rafal Kupiec	7011d456e9	Fix loading CS segment for AMD64 architecture	2024-04-17 16:48:18 +02:00
Rafal Kupiec	4b2d8ded72	No parameters are expected, explicitly	2024-02-20 16:55:12 +01:00
Rafal Kupiec	7727888087	Implement ArFlushTlb() routine	2024-02-04 23:43:38 +01:00
Rafal Kupiec	9ce841e957	Implement memory barriers	2024-02-04 22:10:37 +01:00