70 Commits

Author	SHA1	Message	Date
belliash	f05a262da2	Cleanup XTDK and XTOSKRNL headers	2023-10-29 09:58:47 +01:00
belliash	798e4c1d22	Cleanup MM subsystem headers	2023-10-29 00:52:05 +02:00
belliash	600c86949b	Cleanup RTL subsystem headers	2023-10-29 00:14:01 +02:00
belliash	d920cae481	Fix build by defining more routines used by XTLDR	2023-10-28 23:41:52 +02:00
belliash	ad15c55a39	Cleanup AR subsystem headers	2023-10-28 23:35:34 +02:00
belliash	358b20f1a1	Reorder routines	2023-04-04 22:35:06 +02:00
belliash	e6b64b741a	Initialize thread context for i686	2023-03-15 23:05:18 +01:00
belliash	3afbc7e419	Introduce SIMD save area in place of FN/FX and use anonymous union inside FX_SAVE_AREA structure	2023-03-15 22:19:18 +01:00
belliash	a8fa702b05	Unify KSWITCH_FRAME naming with AMD64	2023-03-15 19:15:31 +01:00
belliash	10ccf67e8e	Add missing forward declarations	2023-03-14 22:50:32 +01:00
belliash	cec8a13e4c	Add context control flags and thread frames for i686 architecture	2023-03-14 22:47:32 +01:00
belliash	70795ae57a	Add EFLAGS and THREAD_ENVIRONMENT_BLOCK for x86	2023-03-05 18:11:57 +01:00
belliash	c5a9253ea8	Implement ArLoadLocalDescriptorTable() routine	2023-03-02 23:04:36 +01:00
belliash	870a6680b0	Add thread information block	2023-03-01 00:14:06 +01:00
belliash	3d42fcc0f5	Add KSWITCH_FRAME definition for i686 architecture	2023-03-01 00:03:20 +01:00
belliash	ef23acc3bc	Add Deferred Procedure Call (DPC) and processor power state related structures	2023-02-27 19:58:47 +01:00
belliash	e41de62dab	Implement ArYieldProcessor() routine	2023-02-27 17:28:20 +01:00
belliash	c8428241dd	Add missing headers containing forward references of MM routines	2023-02-20 22:22:32 +01:00
belliash	b1c2b209e3	Implement RtlGetStackLimits() routine	2023-02-15 20:12:58 +01:00
belliash	18a39f95bc	Add floating save area structure definitions	2023-02-15 20:07:17 +01:00
belliash	2e790bd9b2	Add pages related macros and definitions	2023-02-13 23:01:20 +01:00
belliash	e94cb2d3a7	Processor identification structures	2023-02-10 17:14:12 +01:00
belliash	e645cf664c	Set process and thread information in processor control block	2023-02-09 17:30:24 +01:00
belliash	9132c47cd9	Initial process and thread related structures	2023-02-08 23:40:58 +01:00
belliash	a32e18b237	Implement ArReadFSDualWord() routine	2023-02-07 23:19:22 +01:00
belliash	5eaf7d63a3	Initialize Page Attribute Table	2023-02-05 00:14:34 +01:00
belliash	f37722b6e6	Distinguish ProcessorBlock and ProcessorControlBlock	2023-02-03 19:28:03 +01:00
belliash	269214ed34	Another improvements to GDT	2023-02-03 18:00:37 +01:00
belliash	dc1a94b982	This is 'Processor Block'	2023-02-01 22:02:07 +01:00
belliash	21fbe6febe	Add IDT related definitions	2023-02-01 20:14:10 +01:00
belliash	5bbda188c6	IDT access levels and gate types	2023-02-01 00:51:13 +01:00
belliash	9a1e9b1084	Define TSS offsets	2023-01-30 23:43:10 +01:00
belliash	a761d3125a	Architecture specific initialization prior to processor structures initialization	2023-01-30 20:34:05 +01:00
belliash	6f068513cd	Initial processor block initialization	2023-01-30 19:07:05 +01:00
belliash	ce4e590347	Add missing forward declaration of ArInitializeProcessor() routine	2023-01-29 00:57:06 +01:00
belliash	900e71459a	Add missing x86 descriptor sizes	2023-01-29 00:54:36 +01:00
belliash	27e2fdf4f2	Introduce architecture library as new kernel subsystem and move selected routines into new subsystem	2023-01-28 10:34:55 +01:00
belliash	e94e50b5d9	Implement HlLoadInterruptDescriptorTable() intrinsics for loading IDT	2023-01-26 20:08:57 +01:00
belliash	3ad3149f80	Add descriptor structure definition	2023-01-25 17:42:35 +01:00
belliash	bfc9db8b6d	Unify KGDTENTRY and KIDTENTRY between architectures as much as possible	2023-01-25 17:35:03 +01:00
belliash	3ee759cc27	i686 Interrupt request levels definitions	2023-01-25 17:18:27 +01:00
belliash	7bd67d6210	Add GDT and Segments related definitions for i686	2023-01-25 17:13:24 +01:00
belliash	707dc37868	Fix type of Source parameter in HlLoadSegment() routine	2023-01-24 23:08:48 +01:00
belliash	35aa514f95	Implement HlLoadSegment() intrinsics routine	2023-01-24 19:27:18 +01:00
belliash	d3d8d144a0	Implement HlLoadGlobalDescriptorTable() intrinsic	2023-01-23 20:13:51 +01:00
belliash	f20ab3e52e	Implement HlLoadTaskRegister() for loading TSS segment selector into task register	2023-01-23 15:26:35 +01:00
belliash	fb60625abc	Add more intrinsic routines	2023-01-13 22:32:45 +01:00
belliash	ca1d7ddfe8	Basic context, frames and exceptions definitions	2023-01-07 23:36:50 +01:00
belliash	f74ba62f24	Add GDT, IDT and TSS related structures	2023-01-07 13:33:16 +01:00
belliash	674e69da0e	Cleanup useless externals	2023-01-05 23:38:58 +01:00