perikiyoxd/exectos
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Code Pull Requests Activity
1,430 Commits 5 Branches 0 Tags
d88f9f0a15d8a6bd1c3dc83465738b662bf2a8e5
Commit Graph
110 Commits
Author SHA1 Message Date
harraiken d88f9f0a15 Remove erroneous swapgs and implement proper segment setting 2026-04-01 11:18:28 +02:00
harraiken 154b2062ba Unify GDT selector naming convention 2026-04-01 11:02:05 +02:00
harraiken d00577ac8d Fix previous mode detection by reading CS from the trap frame 2026-03-31 23:10:45 +02:00
harraiken 620fc24cd2 Fix previous mode detection by reading CS from the trap frame and sanitize segment restoration 2026-03-31 20:38:21 +02:00
harraiken 494b615dc2 Fix x64 ABI compliance by aligning stack and reserving shadow space 2026-03-31 20:06:25 +02:00
harraiken d834b7e0c8 Correct kernel stack base calculation for downward growing stacks 2026-03-31 18:59:59 +02:00
harraiken 987b8f45d7 Unify trap handler macro name 2026-03-31 15:53:11 +02:00
harraiken 121f461491 Refactor trap handling to support task gates 2026-03-31 12:58:46 +02:00
harraiken f4b189adef Fix incorrect descriptor type used for NMI TSS 2026-03-30 22:20:09 +02:00
harraiken 40c4860548 Refine LDT setup and restore critical TSS fields for hardware exceptions 2026-03-30 20:29:43 +02:00
harraiken d2a7ae46ac Fix hardware task gate configuration 2026-03-30 20:16:44 +02:00
harraiken 8a02a5aca3 Explicitly load GS and SS registers during segment initialization 2026-03-30 18:43:52 +02:00
harraiken 96df5a80b8 Set CR3 field in TSS to ensure correct page table context on task switches 2026-03-30 14:56:41 +02:00
harraiken 489ef8a514 Update IDT gate types for i686 exception handlers 2026-03-30 13:31:20 +02:00
harraiken 8c6c63465f Use dedicated NMI stack on i686 2026-03-30 11:43:09 +02:00
harraiken a608b26fde Implement NMI stack handling via IST 2026-03-28 20:49:18 +01:00
harraiken 32d3672a51 Generate distinct handlers for CPU traps and hardware interrupts 2026-03-27 20:42:41 +01:00
harraiken 0c17337388 Fix symbol naming convention for i686 trap handlers 2026-03-27 19:23:37 +01:00
harraiken 9c449bed43 Initialize IDT with specific trap handlers for each vector 2026-03-27 19:16:16 +01:00
harraiken 0fed593147 Ensure SS and RSP are saved in trap frame 2026-03-15 17:32:01 +01:00
harraiken 6cdb66cbb3 Ensure SS and ESP are saved in trap frame 2026-03-15 00:33:09 +01:00
harraiken 00b04f5405 Refactor IDT gate setup to use explicit DPL and type fields 2025-10-18 18:29:49 +02:00
harraiken 332e57f305 Add register dump to trap handler 2025-09-25 08:28:02 +02:00
harraiken ae4b95380a Fix AP startup symbol name 2025-09-19 19:23:39 +02:00
harraiken 2b49b23d41 Add trampoline support and move assembler prototypes 2025-09-19 19:07:27 +02:00
harraiken d0577611ca Move asm headers 2025-09-19 13:47:18 +02:00
harraiken 4c380bae1c Fix build by replacing leftover Ar calls 2025-09-19 13:29:15 +02:00
harraiken 1b0468f742 Fix build by replacing leftover Ar calls 2025-09-19 13:26:26 +02:00
harraiken e7425de523 Drop C wrappers and switch to C++ API 2025-09-19 12:56:06 +02:00
harraiken fabf3a3a5e Replace all occurrences of NULL with NULLPTR for unified C and C++ null pointer handling 2025-09-16 15:59:56 +02:00
harraiken 307ec1794c Clean up after migration to C++ 2025-09-16 14:20:20 +02:00
harraiken f4561c1f4f Remove leftover old headers and fix missed spots 2025-09-16 08:46:53 +02:00
harraiken ee97388981 Switch i686 processor structures setup to use class data 2025-09-15 22:50:52 +02:00
harraiken 4592955da1 Migrate HL subsystem to C++ 2025-09-13 19:15:13 +02:00
harraiken 3a11d536d5 Refactor AR subsystem 2025-09-11 20:23:51 +02:00
harraiken 4947f788d5 Migrate KE subsystem to C++ 2025-09-09 23:20:50 +02:00
harraiken 3f5f57ef12 Remove leftover test code 2025-09-08 15:44:12 +02:00
harraiken c8dc2a1407 Migrate AR subsystem to C++ 2025-09-08 15:29:13 +02:00
harraiken c4a7df6f38 Extract trampoline code into a separate file 2025-08-20 20:20:35 +02:00
harraiken 2468d80078 Add trampoline to enable 5-level paging 2025-08-20 00:20:10 +02:00
harraiken e8771dfc5b Use __asm__ to comply with disabled GNU extensions 2025-08-15 00:32:56 +02:00
harraiken d806c8e1f2 Resolve compilation errors due to renamed CPUID requests 2025-08-10 17:12:06 +02:00
harraiken 2ea306097d Resolve compilation errors due to renamed CPUID requests 2025-08-10 17:10:01 +02:00
harraiken ff41b0d4f7 Fix incorrect TSS descriptor limit according to architecture specification 2025-07-28 18:25:47 +02:00
belliash 740df726e9 Implement ArInterruptsEnabled() routine 2024-05-17 23:19:25 +02:00
belliash 5591e1b377 Fix ArGetCpuFlags() routine 2024-05-17 23:16:16 +02:00
belliash 9f1a4f0ced Compose the AMD family and model IDs according to the AMD CPUID manual, section 2 2024-05-14 19:39:07 +02:00
belliash 2a8cc7397e Implement ArGetCpuFlags() routine 2024-05-14 16:26:02 +02:00
belliash 38b0b2ac7d Use correct stack when using preallocated processor structures 2024-05-08 15:57:24 +02:00
belliash 3c3a756771 Allow to initialize CPU with allocated processor structures 2024-05-08 00:02:47 +02:00