15 Commits

Author	SHA1	Message	Date
Aiken Harris	19092eda2e	Rename architecture CPU functions class	2026-05-19 06:45:48 +02:00
Aiken Harris	58669d3074	Refactor memory layout structure	2026-01-29 22:10:26 +01:00
Aiken Harris	446ce920ec	Limit system PTE space mapping to calculated pool size	2026-01-27 16:56:40 +01:00
Aiken Harris	c3607ea943	Add missing annotations	2026-01-14 22:48:25 +01:00
Aiken Harris	7da6bcc75e	Standardize ValidPte setup across architectures	2026-01-14 22:42:14 +01:00
Aiken Harris	3a087766cc	Optimize system PTE deallocation by avoiding immediate and expensive TLB flush	2026-01-05 16:59:35 +01:00
Aiken Harris	410286d012	Replace ULONG with PFN_COUNT in system PTE variables	2026-01-05 16:48:26 +01:00
Aiken Harris	0a43a93f41	Add mechanism to free system PTEs and merge adjacent clusters	2026-01-04 21:11:33 +01:00
Aiken Harris	d891088b1a	Update PTE support to use safe write accessors	2025-12-28 23:39:08 +01:00
Aiken Harris	0880a0f344	Implement PFN database initialization and memory descriptor processing	2025-12-28 23:25:07 +01:00
Aiken Harris	5012c8dc37	Initialize system PTE pools and implement reservation routines	2025-12-23 20:16:08 +01:00
Aiken Harris	24dccf4bed	Make PPE mapping architecture-specific	2025-12-19 20:25:43 +01:00
Aiken Harris	dc23f91110	Split PTE implementation per architecture	2025-12-16 14:08:32 +01:00
Aiken Harris	7f0ca6a948	Compute PTE count per page from entry size	2025-12-15 13:56:39 +01:00
Aiken Harris	36c273ea13	Implement early page table mapping routines	2025-12-15 13:24:02 +01:00