Complete ArpIdentifyProcessor unimplemented logic

- Fixes CPUID VendorName
- Fixes Model on AMD Family 0x19
- Stores raw CPU features to PRCB

sdk/xtdk/amd64/artypes.h

@@ -204,6 +204,13 @@ typedef struct _CPU_IDENTIFICATION
     UCHAR VendorName[13];
 } CPU_IDENTIFICATION, *PCPU_IDENTIFICATION;
 
+/* Processor features */
+typedef struct _CPU_FEATURES
+{
+    CPUID_FEATURES Ecx;
+    CPUID_FEATURES Edx;
+} CPU_FEATURES, *PCPU_FEATURES;
+
 /* CPUID registers */
 typedef struct _CPUID_REGISTERS
 {

sdk/xtdk/amd64/ketypes.h

@@ -498,6 +498,7 @@ typedef struct _KPROCESSOR_CONTROL_BLOCK
     ULONG64 RspBase;
     ULONG_PTR SetMember;
     CPU_IDENTIFICATION CpuId;
+    CPU_FEATURES CpuFeatures;
     KPROCESSOR_STATE ProcessorState;
     KSPIN_LOCK_QUEUE LockQueue[MaximumLock];
     KDPC_DATA DpcData[2];

sdk/xtdk/amd64/xtstruct.h

@@ -21,6 +21,7 @@ typedef enum _PAGE_SIZE PAGE_SIZE, *PPAGE_SIZE;
 /* Architecture-specific structures forward references */
 typedef struct _CONTEXT CONTEXT, *PCONTEXT;
 typedef struct _CPU_IDENTIFICATION CPU_IDENTIFICATION, *PCPU_IDENTIFICATION;
+typedef struct _CPU_FEATURES CPU_FEATURES, *PCPU_FEATURES;
 typedef struct _CPUID_REGISTERS CPUID_REGISTERS, *PCPUID_REGISTERS;
 typedef struct _CPUID_SIGNATURE CPUID_SIGNATURE, *PCPUID_SIGNATURE;
 typedef struct _FLOATING_SAVE_AREA FLOATING_SAVE_AREA, *PFLOATING_SAVE_AREA;

sdk/xtdk/i686/artypes.h

@@ -155,6 +155,13 @@ typedef struct _CPU_IDENTIFICATION
     UCHAR VendorName[13];
 } CPU_IDENTIFICATION, *PCPU_IDENTIFICATION;
 
+/* Processor features */
+typedef struct _CPU_FEATURES
+{
+    CPUID_FEATURES Ecx;
+    CPUID_FEATURES Edx;
+} CPU_FEATURES, *PCPU_FEATURES;
+
 /* CPUID registers */
 typedef struct _CPUID_REGISTERS
 {

sdk/xtdk/i686/ketypes.h

@@ -456,6 +456,7 @@ typedef struct _KPROCESSOR_CONTROL_BLOCK
     UCHAR Number;
     ULONG_PTR SetMember;
     CPU_IDENTIFICATION CpuId;
+    CPU_FEATURES CpuFeatures;
     KPROCESSOR_STATE ProcessorState;
     KSPIN_LOCK_QUEUE LockQueue[MaximumLock];
     ULONG_PTR MultiThreadProcessorSet;

sdk/xtdk/i686/xtstruct.h

@@ -21,6 +21,7 @@ typedef enum _PAGE_SIZE PAGE_SIZE, *PPAGE_SIZE;
 /* Architecture-specific structures forward references */
 typedef struct _CONTEXT CONTEXT, *PCONTEXT;
 typedef struct _CPU_IDENTIFICATION CPU_IDENTIFICATION, *PCPU_IDENTIFICATION;
+typedef struct _CPU_FEATURES CPU_FEATURES, *PCPU_FEATURES;
 typedef struct _CPUID_REGISTERS CPUID_REGISTERS, *PCPUID_REGISTERS;
 typedef struct _CPUID_SIGNATURE CPUID_SIGNATURE, *PCPUID_SIGNATURE;
 typedef struct _FN_SAVE_FORMAT FN_SAVE_FORMAT, *PFN_SAVE_FORMAT;

xtoskrnl/ar/amd64/archsup.S

@@ -102,7 +102,7 @@ ArpTrap\Vector:
     movdqa %xmm0, TrapXmm0(%rbp)
 
     /* Test previous mode and swap GS if needed */
-    movl $0, TrapPreviousMode(%ebp)
+    movl $0, TrapPreviousMode(%rbp)
     mov %cs, %ax
     and $1, %al
     mov %al, TrapPreviousMode(%rbp)

xtoskrnl/ar/amd64/procsup.c

@@ -121,24 +121,22 @@ ArpIdentifyProcessor(VOID)
     PKPROCESSOR_CONTROL_BLOCK Prcb;
     CPUID_REGISTERS CpuRegisters;
     CPUID_SIGNATURE CpuSignature;
-
-    /* Not fully implemented yet */
-    UNIMPLEMENTED;
+    UINT32 VendorNameBytes[3];
 
     /* Get current processor control block */
     Prcb = KeGetCurrentProcessorControlBlock();
 
-    /* Get CPU vendor by issueing CPUID instruction */
+    /* Get CPU vendor by issuing CPUID instruction */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
     ArCpuId(&CpuRegisters);
 
-    /* Store CPU vendor in processor control block */
-    Prcb->CpuId.Vendor = CpuRegisters.Ebx;
-    Prcb->CpuId.VendorName[0] = CpuRegisters.Ebx;
-    Prcb->CpuId.VendorName[4] = CpuRegisters.Edx;
-    Prcb->CpuId.VendorName[8] = CpuRegisters.Ecx;
-    Prcb->CpuId.VendorName[12] = '\0';
+    /* Store CPU vendor name in processor control block */
+    RtlZeroMemory(&Prcb->CpuId.VendorName[0], 13);
+    VendorNameBytes[0] = CpuRegisters.Ebx;
+    VendorNameBytes[1] = CpuRegisters.Edx;
+    VendorNameBytes[2] = CpuRegisters.Ecx;
+    RtlCopyMemory(&Prcb->CpuId.VendorName[0], &VendorNameBytes[0], 12);
 
     /* Get CPU features */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
@@ -151,19 +149,28 @@ ArpIdentifyProcessor(VOID)
     Prcb->CpuId.Model = CpuSignature.Model;
     Prcb->CpuId.Stepping = CpuSignature.Stepping;
 
-    /* CPU vendor specific quirks */
-    if(Prcb->CpuId.Vendor == CPU_VENDOR_AMD)
+    /* Set CPU vendor on processor control block by comparing known vendor names,
+     * along with specific CPU family and model detection quirks */
+    Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN;
+
+    if(RtlCompareMemory(&VendorNameBytes[0], "AuthenticAMD", 12) == 12)
     {
-        /* AMD CPU */
+        Prcb->CpuId.Vendor = CPU_VENDOR_AMD;
+
+        /* AMD CPU specific family and model handling */
         Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
-        if(Prcb->CpuId.Model == 0xF)
+
+        // https://en.wikichip.org/wiki/amd/cpuid - AMD CPUID
+        if(Prcb->CpuId.Model == 0xF || Prcb->CpuId.Family >= 0x19)
         {
             Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
         }
     }
-    else if(Prcb->CpuId.Vendor == CPU_VENDOR_INTEL)
+    else if(RtlCompareMemory(&VendorNameBytes[0], "GenuineIntel", 12) == 12)
     {
-        /* Intel CPU */
+        Prcb->CpuId.Vendor = CPU_VENDOR_INTEL;
+
+        /* Intel CPU specific family and model handling */
         if(Prcb->CpuId.Family == 0xF)
         {
             Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
@@ -174,13 +181,13 @@ ArpIdentifyProcessor(VOID)
             Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
         }
     }
-    else
-    {
-        /* Unknown CPU vendor */
-        Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN;
-    }
 
-    /* TODO: Store a list of CPU features in processor control block */
+    /* Store CPU features in processor control block */
+    RtlZeroMemory(&Prcb->CpuFeatures, sizeof(CPU_FEATURES));
+    RtlCopyMemory(&Prcb->CpuFeatures.Ecx, &CpuRegisters.Ecx, sizeof(UINT32));
+    RtlCopyMemory(&Prcb->CpuFeatures.Edx, &CpuRegisters.Edx, sizeof(UINT32));
+
+    KeDbgPrint(L"CPU %hhu: %s %hu.%hu.%hu\n", Prcb->Number, Prcb->CpuId.VendorName, Prcb->CpuId.Family, Prcb->CpuId.Model, Prcb->CpuId.Stepping);
 }
 
 /**

xtoskrnl/ar/i686/procsup.c

@@ -116,24 +116,22 @@ ArpIdentifyProcessor(VOID)
     PKPROCESSOR_CONTROL_BLOCK Prcb;
     CPUID_REGISTERS CpuRegisters;
     CPUID_SIGNATURE CpuSignature;
-
-    /* Not fully implemented yet */
-    UNIMPLEMENTED;
+    UINT32 VendorNameBytes[3];
 
     /* Get current processor control block */
     Prcb = KeGetCurrentProcessorControlBlock();
 
-    /* Get CPU vendor by issueing CPUID instruction */
+    /* Get CPU vendor by issuing CPUID instruction */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
     ArCpuId(&CpuRegisters);
 
-    /* Store CPU vendor in processor control block */
-    Prcb->CpuId.Vendor = CpuRegisters.Ebx;
-    Prcb->CpuId.VendorName[0] = CpuRegisters.Ebx;
-    Prcb->CpuId.VendorName[4] = CpuRegisters.Edx;
-    Prcb->CpuId.VendorName[8] = CpuRegisters.Ecx;
-    Prcb->CpuId.VendorName[12] = '\0';
+    /* Store CPU vendor name in processor control block */
+    RtlZeroMemory(&Prcb->CpuId.VendorName[0], 13);
+    VendorNameBytes[0] = CpuRegisters.Ebx;
+    VendorNameBytes[1] = CpuRegisters.Edx;
+    VendorNameBytes[2] = CpuRegisters.Ecx;
+    RtlCopyMemory(&Prcb->CpuId.VendorName[0], &VendorNameBytes[0], 12);
 
     /* Get CPU features */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
@@ -146,19 +144,28 @@ ArpIdentifyProcessor(VOID)
     Prcb->CpuId.Model = CpuSignature.Model;
     Prcb->CpuId.Stepping = CpuSignature.Stepping;
 
-    /* CPU vendor specific quirks */
-    if(Prcb->CpuId.Vendor == CPU_VENDOR_AMD)
+    /* Set CPU vendor on processor control block by comparing known vendor names,
+     * along with specific CPU family and model detection quirks */
+    Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN;
+
+    if(RtlCompareMemory(&VendorNameBytes[0], "AuthenticAMD", 12) == 12)
     {
-        /* AMD CPU */
+        Prcb->CpuId.Vendor = CPU_VENDOR_AMD;
+
+        /* AMD CPU specific family and model handling */
         Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
-        if(Prcb->CpuId.Model == 0xF)
+
+        // https://en.wikichip.org/wiki/amd/cpuid - AMD CPUID
+        if(Prcb->CpuId.Model == 0xF || Prcb->CpuId.Family >= 0x19)
         {
             Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
         }
     }
-    else if(Prcb->CpuId.Vendor == CPU_VENDOR_INTEL)
+    else if(RtlCompareMemory(&VendorNameBytes[0], "GenuineIntel", 12) == 12)
     {
-        /* Intel CPU */
+        Prcb->CpuId.Vendor = CPU_VENDOR_INTEL;
+
+        /* Intel CPU specific family and model handling */
         if(Prcb->CpuId.Family == 0xF)
         {
             Prcb->CpuId.Family = Prcb->CpuId.Family + CpuSignature.ExtendedFamily;
@@ -169,13 +176,13 @@ ArpIdentifyProcessor(VOID)
             Prcb->CpuId.Model = Prcb->CpuId.Model + (CpuSignature.ExtendedModel << 4);
         }
     }
-    else
-    {
-        /* Unknown CPU vendor */
-        Prcb->CpuId.Vendor = CPU_VENDOR_UNKNOWN;
-    }
 
-    /* TODO: Store a list of CPU features in processor control block */
+    /* Store CPU features in processor control block */
+    RtlZeroMemory(&Prcb->CpuFeatures, sizeof(CPU_FEATURES));
+    RtlCopyMemory(&Prcb->CpuFeatures.Ecx, &CpuRegisters.Ecx, sizeof(UINT32));
+    RtlCopyMemory(&Prcb->CpuFeatures.Edx, &CpuRegisters.Edx, sizeof(UINT32));
+
+    KeDbgPrint(L"CPU %hhu: %s %hu.%hu.%hu\n", Prcb->Number, Prcb->CpuId.VendorName, Prcb->CpuId.Family, Prcb->CpuId.Model, Prcb->CpuId.Stepping);
 }
 
 /**

xtoskrnl/ke/amd64/kthread.c

@@ -82,7 +82,7 @@ KepInitializeThreadContext(IN PKTHREAD Thread,
         ThreadFrame->TrapFrame.Dr7 = 0;
 
         /* Set initial MXCSR register value */
-        // ThreadFrame->TrapFrame.MxCsr = INITIAL_MXCSR;
+        ThreadFrame->TrapFrame.MxCsr = INITIAL_MXCSR;
 
         /* Initialize exception frame */
         ThreadFrame->ExceptionFrame.P1Home = (ULONG64)StartContext;

xtoskrnl/ke/i686/kthread.c

@@ -80,19 +80,13 @@ KepInitializeThreadContext(IN PKTHREAD Thread,
         ThreadFrame->TrapFrame.Dr6 = 0;
         ThreadFrame->TrapFrame.Dr7 = 0;
 
-        /* Set exception list pointer in the trap frame */
-        // ThreadFrame->TrapFrame.ExceptionList = (PEXCEPTION_REGISTRATION_RECORD) - 1;
-
         /* Set DS, ES and SS segments for user mode */
         ThreadFrame->TrapFrame.SegDs |= RPL_MASK;
         ThreadFrame->TrapFrame.SegEs |= RPL_MASK;
         ThreadFrame->TrapFrame.SegSs |= RPL_MASK;
 
-        /* Set debug mark in the trap frame */
-        // ThreadFrame->TrapFrame.DbgMark = 0x8BADF00D;
-
         /* Set user mode thread in the trap frame */
-        // ThreadFrame->TrapFrame.PreviousMode = UserMode;
+        ThreadFrame->TrapFrame.PreviousMode = UserMode;
     }
     else
     {