forked from xt-sys/exectos
194 lines
8.5 KiB
C
194 lines
8.5 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: sdk/xtdk/hltypes.h
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* DESCRIPTION: XT hardware abstraction layer structures definitions
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#ifndef __XTDK_HLTYPES_H
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#define __XTDK_HLTYPES_H
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#include <xttypes.h>
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/* Default serial port settings */
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#define COMPORT_CLOCK_RATE 0x1C200
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#define COMPORT_WAIT_TIMEOUT 204800
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/* Serial port divisors */
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#define COMPORT_DIV_DLL 0x00 /* Divisor Latch Least */
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#define COMPORT_DIV_DLM 0x01 /* Divisor Latch Most */
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/* Serial port control flags */
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#define COMPORT_FLAG_INIT 0x01 /* Port Initialized */
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#define COMPORT_FLAG_DBR 0x02 /* Default Baud Rate */
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#define COMPORT_FLAG_MC 0x04 /* Modem Control */
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/* Serial port Fifo Control Register (FCR) access masks */
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#define COMPORT_FCR_DISABLE 0x00 /* Disable */
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#define COMPORT_FCR_ENABLE 0x01 /* Enable */
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#define COMPORT_FCR_RCVR_RESET 0x02 /* Receiver Reset */
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#define COMPORT_FCR_TXMT_RESET 0x04 /* Transmitter Reset */
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/* Serial port Line Control Register (LCR) access masks */
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#define COMPORT_LCR_1STOP 0x00 /* 1 Stop Bit */
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#define COMPORT_LCR_2STOP 0x04 /* 2 Stop Bits */
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#define COMPORT_LCR_5DATA 0x00 /* 5 Data Bits */
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#define COMPORT_LCR_6DATA 0x01 /* 6 Data Bits */
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#define COMPORT_LCR_7DATA 0x02 /* 7 Data Bits */
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#define COMPORT_LCR_8DATA 0x03 /* 8 Data Bits */
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#define COMPORT_LCR_PARN 0x00 /* None Parity */
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#define COMPORT_LCR_PARO 0x08 /* Odd Parity */
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#define COMPORT_LCR_PARE 0x18 /* Even Parity */
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#define COMPORT_LCR_PARM 0x28 /* Mark Parity */
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#define COMPORT_LCR_PARS 0x38 /* Space Parity */
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#define COMPORT_LCR_BREAK 0x40 /* Break */
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#define COMPORT_LCR_DLAB 0x80 /* Divisor Latch Access Bit */
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/* Serial port Line Status Register (LSR) access masks */
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#define COMPORT_LSR_DIS 0x00 /* Disable */
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#define COMPORT_LSR_DR 0x01 /* Data Ready */
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#define COMPORT_LSR_OE 0x02 /* Overrun Error */
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#define COMPORT_LSR_PE 0x04 /* Parity Error */
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#define COMPORT_LSR_FE 0x08 /* Framing Error */
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#define COMPORT_LSR_BI 0x10 /* Break Interrupt */
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#define COMPORT_LSR_THRE 0x20 /* Transmit Holding Register Empty */
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#define COMPORT_LSR_TEMPTY 0x40 /* Transmitter Empty */
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#define COMPORT_LSR_FIFOE 0x80 /* FIFO Error */
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/* Serial port Modem Control Register (MCR) access masks */
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#define COMPORT_MCR_DTR 0x01 /* Data Terminal Ready */
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#define COMPORT_MCR_RTS 0x02 /* Ready To Send */
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#define COMPORT_MCR_OUT1 0x04 /* Generic Output 1 */
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#define COMPORT_MCR_OUT2 0x08 /* Generic Output 2 */
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#define COMPORT_MCR_NOM 0x0F /* Normal Operation Mode */
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#define COMPORT_MCR_LOOP 0x10 /* Loopback Testing Mode */
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/* Serial port Modem Status Register (MSR) access masks */
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#define COMPORT_MSR_DCTS 0x01 /* Delta Clear To Send */
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#define COMPORT_MSR_DDSR 0x02 /* Delta Data Set Ready */
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#define COMPORT_MSR_DTRRTS 0x03 /* DTR and RTS */
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#define COMPORT_MSR_TERI 0x04 /* Trailing Edge Ring Indicator */
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#define COMPORT_MSR_DDCD 0x08 /* Delta Data Carrier Detect */
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#define COMPORT_MSR_CTS 0x10 /* Clear To Send */
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#define COMPORT_MSR_DSR 0x20 /* Data Set Ready */
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#define COMPORT_MSR_RI 0x40 /* Ring Indicator */
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#define COMPORT_MSR_DCD 0x80 /* Data Carrier Detect */
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#define COMPORT_MSR_DSRCTSCD 0xB0 /* DSR, CTS and CD */
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#define COMPORT_MSR_TST 0xAE /* Test Pattern */
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/* Serial port offsets of the various registers */
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#define COMPORT_REG_RBR 0x00 /* Receive Buffer Register */
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#define COMPORT_REG_THR 0x00 /* Transmit Holding Register */
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#define COMPORT_REG_IER 0x01 /* Interrupt Enable Register */
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#define COMPORT_REG_IIR 0x02 /* Interrupt Identity Register */
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#define COMPORT_REG_FCR 0x02 /* FIFO Control Register */
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#define COMPORT_REG_LCR 0x03 /* Line Control Register */
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#define COMPORT_REG_MCR 0x04 /* Modem Control Register */
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#define COMPORT_REG_LSR 0x05 /* Line Status Register */
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#define COMPORT_REG_MSR 0x06 /* Modem Status Register */
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#define COMPORT_REG_SR 0x07 /* Scratch Register */
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/* APIC Register Address Map */
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typedef enum _APIC_REGISTER
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{
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APIC_ID = 0x02, /* APIC ID Register */
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APIC_VER = 0x03, /* APIC Version Register */
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APIC_TPR = 0x08, /* Task Priority Register */
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APIC_APR = 0x09, /* Arbitration Priority Register */
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APIC_PPR = 0x0A, /* Processor Priority Register (R) */
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APIC_EOI = 0x0B, /* EOI Register */
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APIC_RRR = 0x0C, /* Remote Read Register */
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APIC_LDR = 0x0D, /* Logical Destination Register */
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APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
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APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
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APIC_ISR = 0x10, /* Interrupt Service Register*/
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APIC_TMR = 0x18, /* Trigger Mode Register */
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APIC_IRR = 0x20, /* Interrupt Request Register */
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APIC_ESR = 0x28, /* Error Status Register */
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APIC_ICR0 = 0x30, /* Interrupt Command Register */
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APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
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APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
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APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
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APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
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APIC_LINT0 = 0x35, /* LINT0 Local Vector Table */
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APIC_LINT1 = 0x36, /* LINT1 Local Vector Table */
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APIC_ERRLVTR = 0x37, /* Error Local Vector Table */
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APIC_TICR = 0x38, /* Initial Count Register for Timer */
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APIC_TCCR = 0x39, /* Current Count Register for Timer */
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APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */
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APIC_EAFR = 0x40, /* extended APIC Feature register */
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APIC_EACR = 0x41, /* Extended APIC Control Register */
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APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */
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APIC_EXT0LVTR = 0x50, /* Extended Interrupt 0 Local Vector Table */
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APIC_EXT1LVTR = 0x51, /* Extended Interrupt 1 Local Vector Table */
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APIC_EXT2LVTR = 0x52, /* Extended Interrupt 2 Local Vector Table */
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APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
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} APIC_REGISTER, *PAPIC_REGISTER;
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/* APIC mode list */
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typedef enum _HAL_APIC_MODE
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{
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APIC_MODE_COMPAT,
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APIC_MODE_X2APIC
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} HAL_APIC_MODE, *PHAL_APIC_MODE;
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/* Serial (COM) port initial state */
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typedef struct _CPPORT
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{
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PUCHAR Address;
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ULONG Baud;
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USHORT Flags;
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} CPPORT, *PCPPORT;
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/* HAL framebuffer data structure */
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typedef struct _HAL_FRAMEBUFFER_DATA
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{
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BOOLEAN Initialized;
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PVOID Address;
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ULONG_PTR BufferSize;
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UINT Width;
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UINT Height;
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UINT PixelsPerScanLine;
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UINT BitsPerPixel;
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UINT Pitch;
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PVOID Font;
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} HAL_FRAMEBUFFER_DATA, *PHAL_FRAMEBUFFER_DATA;
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/* SMBIOS table header structure */
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typedef struct _SMBIOS_TABLE_HEADER
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{
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UCHAR Signature[4];
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UCHAR Checksum;
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UCHAR Length;
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UCHAR MajorVersion;
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UCHAR MinorVersion;
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USHORT MaxStructureSize;
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UCHAR EntryPointRevision;
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UCHAR Reserved[5];
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UCHAR Signature2[5];
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UCHAR IntermediateChecksum;
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USHORT TableLength;
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ULONG TableAddress;
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USHORT NumberOfStructures;
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UCHAR BcdRevision;
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} SMBIOS_TABLE_HEADER, *PSMBIOS_TABLE_HEADER;
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/* SMBIOS3 table header structure */
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typedef struct _SMBIOS3_TABLE_HEADER
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{
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UCHAR Signature[5];
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UCHAR Checksum;
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UCHAR Length;
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UCHAR MajorVersion;
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UCHAR MinorVersion;
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UCHAR DocRevision;
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UCHAR EntryPointRevision;
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UCHAR Reserved;
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ULONG MaxStructureSize;
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ULONGLONG TableAddress;
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} SMBIOS3_TABLE_HEADER, *PSMBIOS3_TABLE_HEADER;
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#endif /* __XTDK_HLTYPES_H */
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