forked from xt-sys/exectos
338 lines
11 KiB
C
338 lines
11 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: sdk/xtdk/i686/hltypes.h
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* DESCRIPTION: XT hardware abstraction layer structures definitions specific to i686 architecture
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#ifndef __XTDK_I686_HLTYPES_H
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#define __XTDK_I686_HLTYPES_H
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#include <xtdefs.h>
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#include <xtstruct.h>
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#include <xttypes.h>
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#include ARCH_HEADER(xtstruct.h)
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/* APIC base addresses */
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#define APIC_BASE 0xFFFE0000
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#define APIC_LAPIC_MSR_BASE 0x0000001B
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#define APIC_X2APIC_MSR_BASE 0x00000800
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/* APIC vector definitions */
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#define APIC_VECTOR_ZERO 0x00
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#define APIC_VECTOR_SPURIOUS 0x1F
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#define APIC_VECTOR_APC 0x3D
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#define APIC_VECTOR_DPC 0x41
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#define APIC_VECTOR_REBOOT 0x50
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#define APIC_VECTOR_DEVICE1 0x51
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#define APIC_VECTOR_DEVICE2 0x61
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#define APIC_VECTOR_DEVICE3 0x71
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#define APIC_VECTOR_DEVICE4 0x81
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#define APIC_VECTOR_DEVICE5 0x91
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#define APIC_VECTOR_DEVICE6 0xA1
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#define APIC_VECTOR_DEVICE7 0xB1
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#define APIC_VECTOR_GENERIC 0xC1
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#define APIC_VECTOR_SYNC 0xC1
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#define APIC_VECTOR_CLOCK 0xD1
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#define APIC_VECTOR_IPI 0xE1
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#define APIC_VECTOR_ERROR 0xE3
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#define APIC_VECTOR_POWERFAIL 0xEF
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#define APIC_VECTOR_PROFILE 0xFD
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#define APIC_VECTOR_PERF 0xFE
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#define APIC_VECTOR_NMI 0xFF
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/* APIC destination formats */
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#define APIC_DF_FLAT 0xFFFFFFFF
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#define APIC_DF_CLUSTER 0x0FFFFFFF
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0x00000000
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#define APIC_DM_LOWPRIO 0x00000100
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#define APIC_DM_SMI 0x00000200
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#define APIC_DM_REMOTE 0x00000300
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#define APIC_DM_NMI 0x00000400
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#define APIC_DM_INIT 0x00000500
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#define APIC_DM_STARTUP 0x00000600
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#define APIC_DM_EXTINT 0x00000700
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/* APIC trigger modes */
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#define APIC_TGM_EDGE 0
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#define APIC_TGM_LEVEL 1
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/* APIC LDR (Logical Destination Register) shifts */
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#define APIC_X2APIC_LDR_SHIFT 16
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#define APIC_XAPIC_LDR_SHIFT 24
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/* Maximum number of I/O APICs */
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#define APIC_MAX_IOAPICS 64
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/* 8259/ISP PIC ports definitions */
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#define PIC1_CONTROL_PORT 0x20
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#define PIC1_DATA_PORT 0x21
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#define PIC1_ELCR_PORT 0x04D0
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#define PIC2_CONTROL_PORT 0xA0
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#define PIC2_DATA_PORT 0xA1
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#define PIC2_ELCR_PORT 0x04D1
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/* PIC vector definitions */
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#define PIC1_VECTOR_SPURIOUS 0x37
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/* Serial ports information */
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#define COMPORT_ADDRESS {0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}
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#define COMPORT_COUNT 8
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/* Initial stall factor */
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#define INITIAL_STALL_FACTOR 100
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/* APIC Register Address Map */
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typedef enum _APIC_REGISTER
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{
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APIC_ID = 0x02, /* APIC ID Register */
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APIC_VER = 0x03, /* APIC Version Register */
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APIC_TPR = 0x08, /* Task Priority Register */
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APIC_APR = 0x09, /* Arbitration Priority Register */
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APIC_PPR = 0x0A, /* Processor Priority Register (R) */
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APIC_EOI = 0x0B, /* EOI Register */
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APIC_RRR = 0x0C, /* Remote Read Register */
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APIC_LDR = 0x0D, /* Logical Destination Register */
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APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */
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APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */
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APIC_ISR = 0x10, /* Interrupt Service Register*/
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APIC_TMR = 0x18, /* Trigger Mode Register */
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APIC_IRR = 0x20, /* Interrupt Request Register */
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APIC_ESR = 0x28, /* Error Status Register */
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APIC_ICR0 = 0x30, /* Interrupt Command Register */
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APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */
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APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */
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APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */
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APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */
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APIC_LINT0 = 0x35, /* LINT0 Local Vector Table */
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APIC_LINT1 = 0x36, /* LINT1 Local Vector Table */
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APIC_ERRLVTR = 0x37, /* Error Local Vector Table */
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APIC_TICR = 0x38, /* Initial Count Register for Timer */
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APIC_TCCR = 0x39, /* Current Count Register for Timer */
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APIC_TDCR = 0x3E, /* Timer Divide Configuration Register */
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APIC_EAFR = 0x40, /* extended APIC Feature register */
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APIC_EACR = 0x41, /* Extended APIC Control Register */
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APIC_SEOI = 0x42, /* Specific End Of Interrupt Register */
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APIC_EXT0LVTR = 0x50, /* Extended Interrupt 0 Local Vector Table */
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APIC_EXT1LVTR = 0x51, /* Extended Interrupt 1 Local Vector Table */
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APIC_EXT2LVTR = 0x52, /* Extended Interrupt 2 Local Vector Table */
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APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */
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} APIC_REGISTER, *PAPIC_REGISTER;
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/* APIC mode list */
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typedef enum _APIC_MODE
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{
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APIC_MODE_COMPAT,
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APIC_MODE_X2APIC
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} APIC_MODE, *PAPIC_MODE;
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/* APIC destination short-hand enumeration list */
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typedef enum _APIC_DSH
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{
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APIC_DSH_Destination,
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APIC_DSH_Self,
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APIC_DSH_AllIncludingSelf,
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APIC_DSH_AllExclusingSelf
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} APIC_DSH, *PAPIC_DSH;
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/* APIC message type enumeration list */
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typedef enum _APIC_MT
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{
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APIC_MT_Fixed,
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APIC_MT_LowestPriority,
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APIC_MT_SMI,
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APIC_MT_RemoteRead,
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APIC_MT_NMI,
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APIC_MT_INIT,
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APIC_MT_Startup,
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APIC_MT_ExtInt,
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} APIC_MT, *PAPIC_MT;
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/* I8259 PIC interrupt mode enumeration list */
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typedef enum _PIC_I8259_ICW1_INTERRUPT_MODE
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{
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EdgeTriggered,
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LevelTriggered
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} PIC_I8259_ICW1_INTERRUPT_MODE, *PPIC_I8259_ICW1_INTERRUPT_MODE;
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/* I8259 PIC interval enumeration list */
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typedef enum _PIC_I8259_ICW1_INTERVAL
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{
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Interval8,
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Interval4
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} PIC_I8259_ICW1_INTERVAL, *PPIC_I8259_ICW1_INTERVAL;
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/* I8259 PIC operating mode enumeration list */
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typedef enum _PIC_I8259_ICW1_OPERATING_MODE
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{
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Cascade,
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Single
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} PIC_I8259_ICW1_OPERATING_MODE, *PPIC_I8259_ICW1_OPERATING_MODE;
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/* I8259 PIC buffered mode enumeration list */
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typedef enum _PIC_I8259_ICW4_BUFFERED_MODE
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{
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NonBuffered,
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NonBuffered2,
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BufferedSlave,
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BufferedMaster
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} PIC_I8259_ICW4_BUFFERED_MODE, *PPIC_I8259_ICW4_BUFFERED_MODE;
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/* I8259 PIC End Of Interrupt (EOI) mode enumeration list */
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typedef enum _PIC_I8259_ICW4_EOI_MODE
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{
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NormalEoi,
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AutomaticEoi
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} PIC_I8259_ICW4_EOI_MODE, *PPIC_I8259_ICW4_EOI_MODE;
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/* I8259 PIC system mode enumeration list */
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typedef enum _PIC_I8259_ICW4_SYSTEM_MODE
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{
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Mcs8085Mode,
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New8086Mode
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} PIC_I8259_ICW4_SYSTEM_MODE, *PPIC_I8259_ICW4_SYSTEM_MODE;
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/* APIC Base Register */
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typedef union _APIC_BASE_REGISTER
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{
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ULONGLONG LongLong;
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struct
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{
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ULONGLONG Reserved1:8;
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ULONGLONG BootStrapProcessor:1;
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ULONGLONG Reserved2:1;
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ULONGLONG ExtendedMode:1;
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ULONGLONG Enable:1;
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ULONGLONG BaseAddress:40;
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ULONGLONG Reserved3:12;
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};
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} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER;
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/* APIC Command Register */
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typedef union _APIC_COMMAND_REGISTER
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{
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ULONGLONG LongLong;
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struct
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{
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ULONG Long0;
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ULONG Long1;
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};
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struct
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{
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ULONGLONG Vector:8;
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ULONGLONG MessageType:3;
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ULONGLONG DestinationMode:1;
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ULONGLONG DeliveryStatus:1;
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ULONGLONG ReservedMBZ:1;
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ULONGLONG Level:1;
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ULONGLONG TriggerMode:1;
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ULONGLONG RemoteReadStatus:2;
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ULONGLONG DestinationShortHand:2;
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ULONGLONG Reserved2MBZ:36;
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ULONGLONG Destination:8;
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};
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} APIC_COMMAND_REGISTER, *PAPIC_COMMAND_REGISTER;
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/* APIC Local Vector Table (LVT) Register */
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typedef union _APIC_LVT_REGISTER
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG MessageType:3;
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ULONG Reserved1:1;
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ULONG DeliveryStatus:1;
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ULONG Reserved2:1;
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ULONG RemoteIRR:1;
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ULONG TriggerMode:1;
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ULONG Mask:1;
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ULONG TimerMode:1;
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ULONG Reserved3:13;
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};
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} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
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/* APIC Spurious Register */
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typedef union _APIC_SPURIOUS_REGISTER
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{
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ULONG Long;
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struct
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{
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ULONG Vector:8;
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ULONG SoftwareEnable:1;
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ULONG CoreChecking:1;
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ULONG Reserved:22;
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};
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} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
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/* I8259 PIC register structure */
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typedef union _PIC_I8259_ICW1
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{
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struct
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{
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UCHAR NeedIcw4:1;
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UCHAR OperatingMode:1;
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UCHAR Interval:1;
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UCHAR InterruptMode:1;
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UCHAR Init:1;
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UCHAR InterruptVectorAddress:3;
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};
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UCHAR Bits;
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} PIC_I8259_ICW1, *PPIC_I8259_ICW1;
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/* I8259 PIC register structure */
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typedef union _PIC_I8259_ICW2
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{
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struct
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{
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UCHAR Sbz:3;
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UCHAR InterruptVector:5;
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};
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UCHAR Bits;
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} PIC_I8259_ICW2, *PPIC_I8259_ICW2;
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/* I8259 PIC register structure */
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typedef union _PIC_I8259_ICW3
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{
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union
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{
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struct
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{
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UCHAR SlaveIrq0:1;
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UCHAR SlaveIrq1:1;
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UCHAR SlaveIrq2:1;
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UCHAR SlaveIrq3:1;
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UCHAR SlaveIrq4:1;
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UCHAR SlaveIrq5:1;
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UCHAR SlaveIrq6:1;
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UCHAR SlaveIrq7:1;
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};
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struct
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{
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UCHAR SlaveId:3;
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UCHAR Reserved:5;
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};
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};
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UCHAR Bits;
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} PIC_I8259_ICW3, *PPIC_I8259_ICW3;
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/* I8259 PIC register structure */
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typedef union _PIC_I8259_ICW4
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{
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struct
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{
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UCHAR SystemMode:1;
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UCHAR EoiMode:1;
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UCHAR BufferedMode:2;
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UCHAR SpecialFullyNestedMode:1;
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UCHAR Reserved:3;
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};
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UCHAR Bits;
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} PIC_I8259_ICW4, *PPIC_I8259_ICW4;
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#endif /* __XTDK_I686_HLTYPES_H */
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