forked from xt-sys/exectos
233 lines
10 KiB
C
233 lines
10 KiB
C
/**
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* PROJECT: ExectOS
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* COPYRIGHT: See COPYING.md in the top level directory
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* FILE: sdk/xtdk/amd64/artypes.h
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* DESCRIPTION: AMD64 architecture library structure definitions
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* DEVELOPERS: Rafal Kupiec <belliash@codingworkshop.eu.org>
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*/
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#ifndef __XTDK_AMD64_ARTYPES_H
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#define __XTDK_AMD64_ARTYPES_H
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#include <xtdefs.h>
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#include <xtstruct.h>
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#include <xttypes.h>
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/* Control Register 0 constants */
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#define CR0_PE 0x00000001
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#define CR0_MP 0x00000002
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#define CR0_EM 0x00000004
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#define CR0_TS 0x00000008
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#define CR0_ET 0x00000010
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#define CR0_NE 0x00000020
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#define CR0_WP 0x00010000
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#define CR0_AM 0x00040000
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#define CR0_NW 0x20000000
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#define CR0_CD 0x40000000
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#define CR0_PG 0x80000000
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/* Control Register 4 constants */
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#define CR4_VME 0x00000001
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#define CR4_PVI 0x00000002
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#define CR4_TSD 0x00000004
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#define CR4_DE 0x00000008
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#define CR4_PSE 0x00000010
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#define CR4_PAE 0x00000020
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#define CR4_MCE 0x00000040
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#define CR4_PGE 0x00000080
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#define CR4_PCE 0x00000100
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#define CR4_FXSR 0x00000200
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#define CR4_XMMEXCPT 0x00000400
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#define CR4_LA57 0x00001000
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#define CR4_RESERVED1 0x00001800
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#define CR4_VMXE 0x00002000
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#define CR4_SMXE 0x00004000
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#define CR4_RESERVED2 0x00018000
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#define CR4_XSAVE 0x00020000
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#define CR4_RESERVED3 0xFFFC0000
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/* Descriptors size */
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#define GDT_ENTRIES 128
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#define IDT_ENTRIES 256
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/* Initial MXCSR control */
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#define INITIAL_MXCSR 0x1F80
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/* Page Attributes Table types */
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#define PAT_TYPE_STRONG_UC 0ULL
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#define PAT_TYPE_USWC 1ULL
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#define PAT_TYPE_WT 4ULL
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#define PAT_TYPE_WP 5ULL
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#define PAT_TYPE_WB 6ULL
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#define PAT_TYPE_WEAK_UC 7ULL
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/* Segment defintions */
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#define SEGMENT_CS 0x2E
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#define SEGMENT_DS 0x3E
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#define SEGMENT_ES 0x26
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#define SEGMENT_SS 0x36
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#define SEGMENT_FS 0x64
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#define SEGMENT_GS 0x65
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/* MSR values */
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#define X86_MSR_SYSENTER_CS 0x00000174
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#define X86_MSR_SYSENTER_ESP 0x00000175
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#define X86_MSR_SYSENTER_EIP 0x00000176
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#define X86_MSR_POWER_CONTROL 0x000001FC
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#define X86_MSR_PAT 0x00000277
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#define X86_MSR_EFER 0xC0000080
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#define X86_MSR_STAR 0xC0000081
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#define X86_MSR_LSTAR 0xC0000082
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#define X86_MSR_CSTAR 0xC0000083
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#define X86_MSR_FMASK 0xC0000084
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#define X86_MSR_FSBASE 0xC0000100
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#define X86_MSR_GSBASE 0xC0000101
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#define X86_MSR_KERNEL_GSBASE 0xC0000102
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/* Processor features in the EFER MSR */
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#define X86_MSR_EFER_SCE (1 << 0)
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#define X86_MSR_EFER_LME (1 << 8)
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#define X86_MSR_EFER_LMA (1 << 10)
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#define X86_MSR_EFER_NXE (1 << 11)
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#define X86_MSR_EFER_SVME (1 << 12)
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/* X86 EFLAG bit masks definitions */
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#define X86_EFLAGS_NF_MASK 0x00000000 /* None */
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#define X86_EFLAGS_CF_MASK 0x00000001 /* Carry */
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#define X86_EFLAGS_PF_MASK 0x00000004 /* Parity */
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#define X86_EFALGS_AF_MASK 0x00000010 /* Aux Carry */
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#define X86_EFLAGS_ZF_MASK 0x00000040 /* Zero */
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#define X86_EFLAGS_SF_MASK 0x00000080 /* Sign */
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#define X86_EFLAGS_TF_MASK 0x00000100 /* Trap */
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#define X86_EFLAGS_IF_MASK 0x00000200 /* Interrupt */
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#define X86_EFLAGS_DF_MASK 0x00000400 /* Direction */
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#define X86_EFLAGS_OF_MASK 0x00000800 /* Overflow */
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#define X86_EFLAGS_IOPL_MASK 0x00003000 /* I/O Privilege */
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#define X86_EFLAGS_NT_MASK 0x00004000 /* Nested Task */
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#define X86_EFLAGS_SIGN_MASK 0x00008000 /* Sign */
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#define X86_EFLAGS_RF_MASK 0x00010000 /* Resume */
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#define X86_EFLAGS_V86_MASK 0x00020000 /* Virtual 8086 */
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#define X86_EFLAGS_AC_MASK 0x00040000 /* Alignment Check */
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#define X86_EFLAGS_VIF_MASK 0x00080000 /* Virtual Interrupt */
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#define X86_EFLAGS_VIP_MASK 0x00100000 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_ID_MASK 0x00200000 /* Identification */
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/* CPU vendor enumeration list */
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typedef enum _CPU_VENDOR
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{
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CPU_VENDOR_AMD = 0x68747541,
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CPU_VENDOR_INTEL = 0x756E6547,
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CPU_VENDOR_UNKNOWN = 0xFFFFFFFF
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} CPU_VENDOR, *PCPU_VENDOR;
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/* CPUID features enumeration list */
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typedef enum _CPUID_FEATURES
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{
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CPUID_FEATURES_ECX_SSE3 = 1 << 0,
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CPUID_FEATURES_ECX_PCLMUL = 1 << 1,
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CPUID_FEATURES_ECX_DTES64 = 1 << 2,
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CPUID_FEATURES_ECX_MONITOR = 1 << 3,
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CPUID_FEATURES_ECX_DS_CPL = 1 << 4,
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CPUID_FEATURES_ECX_VMX = 1 << 5,
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CPUID_FEATURES_ECX_SMX = 1 << 6,
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CPUID_FEATURES_ECX_EST = 1 << 7,
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CPUID_FEATURES_ECX_TM2 = 1 << 8,
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CPUID_FEATURES_ECX_SSSE3 = 1 << 9,
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CPUID_FEATURES_ECX_CID = 1 << 10,
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CPUID_FEATURES_ECX_SDBG = 1 << 11,
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CPUID_FEATURES_ECX_FMA = 1 << 12,
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CPUID_FEATURES_ECX_CX16 = 1 << 13,
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CPUID_FEATURES_ECX_XTPR = 1 << 14,
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CPUID_FEATURES_ECX_PDCM = 1 << 15,
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CPUID_FEATURES_ECX_PCID = 1 << 17,
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CPUID_FEATURES_ECX_DCA = 1 << 18,
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CPUID_FEATURES_ECX_SSE4_1 = 1 << 19,
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CPUID_FEATURES_ECX_SSE4_2 = 1 << 20,
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CPUID_FEATURES_ECX_X2APIC = 1 << 21,
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CPUID_FEATURES_ECX_MOVBE = 1 << 22,
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CPUID_FEATURES_ECX_POPCNT = 1 << 23,
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CPUID_FEATURES_ECX_TSC = 1 << 24,
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CPUID_FEATURES_ECX_AES = 1 << 25,
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CPUID_FEATURES_ECX_XSAVE = 1 << 26,
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CPUID_FEATURES_ECX_OSXSAVE = 1 << 27,
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CPUID_FEATURES_ECX_AVX = 1 << 28,
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CPUID_FEATURES_ECX_F16C = 1 << 29,
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CPUID_FEATURES_ECX_RDRAND = 1 << 30,
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CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31,
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CPUID_FEATURES_EDX_FPU = 1 << 0,
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CPUID_FEATURES_EDX_VME = 1 << 1,
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CPUID_FEATURES_EDX_DE = 1 << 2,
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CPUID_FEATURES_EDX_PSE = 1 << 3,
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CPUID_FEATURES_EDX_TSC = 1 << 4,
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CPUID_FEATURES_EDX_MSR = 1 << 5,
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CPUID_FEATURES_EDX_PAE = 1 << 6,
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CPUID_FEATURES_EDX_MCE = 1 << 7,
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CPUID_FEATURES_EDX_CX8 = 1 << 8,
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CPUID_FEATURES_EDX_APIC = 1 << 9,
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CPUID_FEATURES_EDX_SEP = 1 << 11,
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CPUID_FEATURES_EDX_MTRR = 1 << 12,
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CPUID_FEATURES_EDX_PGE = 1 << 13,
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CPUID_FEATURES_EDX_MCA = 1 << 14,
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CPUID_FEATURES_EDX_CMOV = 1 << 15,
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CPUID_FEATURES_EDX_PAT = 1 << 16,
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CPUID_FEATURES_EDX_PSE36 = 1 << 17,
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CPUID_FEATURES_EDX_PSN = 1 << 18,
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CPUID_FEATURES_EDX_CLFLUSH = 1 << 19,
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CPUID_FEATURES_EDX_DS = 1 << 21,
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CPUID_FEATURES_EDX_ACPI = 1 << 22,
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CPUID_FEATURES_EDX_MMX = 1 << 23,
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CPUID_FEATURES_EDX_FXSR = 1 << 24,
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CPUID_FEATURES_EDX_SSE = 1 << 25,
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CPUID_FEATURES_EDX_SSE2 = 1 << 26,
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CPUID_FEATURES_EDX_SS = 1 << 27,
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CPUID_FEATURES_EDX_HTT = 1 << 28,
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CPUID_FEATURES_EDX_TM = 1 << 29,
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CPUID_FEATURES_EDX_IA64 = 1 << 30,
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CPUID_FEATURES_EDX_PBE = 1 << 31
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} CPUID_FEATURES, *PCPUID_FEATURES;
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/* CPUID requests */
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typedef enum _CPUID_REQUESTS
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{
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CPUID_GET_VENDOR_STRING,
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CPUID_GET_CPU_FEATURES,
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CPUID_GET_TLB,
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CPUID_GET_SERIAL
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} CPUID_REQUESTS, *PCPUID_REQUESTS;
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/* Processor identification information */
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typedef struct _CPU_IDENTIFICATION
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{
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USHORT Family;
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USHORT Model;
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USHORT Stepping;
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CPU_VENDOR Vendor;
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UCHAR VendorName[13];
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} CPU_IDENTIFICATION, *PCPU_IDENTIFICATION;
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/* CPUID registers */
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typedef struct _CPUID_REGISTERS
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{
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UINT32 Leaf;
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UINT32 SubLeaf;
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UINT32 Eax;
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UINT32 Ebx;
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UINT32 Ecx;
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UINT32 Edx;
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} CPUID_REGISTERS, *PCPUID_REGISTERS;
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/* CPU signature read from CPUID structure definition */
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typedef struct _CPUID_SIGNATURE
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{
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ULONG Stepping:4;
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ULONG Model:4;
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ULONG Family:4;
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ULONG Unused1:4;
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ULONG ExtendedModel:4;
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ULONG ExtendedFamily:8;
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ULONG Unused2:4;
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} CPU_SIGNATURE, *PCPU_SIGNATURE;
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#endif /* __XTDK_AMD64_ARTYPES_H */
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