Add PCI Type0 and Type1 device structure definitions
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@ -58,6 +58,32 @@
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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/* PCI bridge control registers */
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typedef struct _PCI_BRIDGE_CONTROL_REGISTER
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{
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UINT Bar[2];
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatencyTimer;
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UCHAR IoBase;
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UCHAR IoLimit;
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USHORT SecondaryStatus;
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USHORT MemoryBase;
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USHORT MemoryLimit;
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USHORT PrefetchableMemoryBase;
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USHORT PrefetchableMemoryLimit;
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UINT PrefetchableBaseUpper32;
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UINT PrefetchableLimitUpper32;
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USHORT IoBaseUpper16;
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USHORT IoLimitUpper16;
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UINT Reserved;
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UINT ExpansionRomBAR;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} PCI_BRIDGE_CONTROL_REGISTER, *PPCI_BRIDGE_CONTROL_REGISTER;
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/* PCI and PCI-E common header structure */
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/* PCI and PCI-E common header structure */
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typedef struct _PCI_COMMON_HEADER
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typedef struct _PCI_COMMON_HEADER
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{
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{
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@ -144,4 +170,48 @@ typedef struct _PCI_COMMON_CONFIG
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UCHAR DeviceSpecific[192];
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UCHAR DeviceSpecific[192];
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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/* PCI device independent region structure */
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typedef struct _PCI_DEVICE_INDEPENDENT_REGION
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{
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USHORT VendorId;
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USHORT DeviceId;
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USHORT Command;
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USHORT Status;
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UCHAR RevisionID;
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UCHAR ClassCode[3];
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UCHAR CacheLineSize;
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UCHAR LaytencyTimer;
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UCHAR HeaderType;
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UCHAR BIST;
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} PCI_DEVICE_INDEPENDENT_REGION, *PPCI_DEVICE_INDEPENDENT_REGION;
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/* PCI device header type region structure */
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typedef struct _PCI_DEVICE_HEADER_TYPE_REGION
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{
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UINT Bar[6];
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UINT CISPtr;
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USHORT SubsystemVendorID;
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USHORT SubsystemID;
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UINT ExpansionRomBar;
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UINT Reserved[2];
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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UCHAR MinGnt;
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UCHAR MaxLat;
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} PCI_DEVICE_HEADER_TYPE_REGION, *PPCI_DEVICE_HEADER_TYPE_REGION;
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/* PCI device type 0 structure */
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typedef struct _PCI_TYPE0_DEVICE
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{
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PCI_DEVICE_INDEPENDENT_REGION Hdr;
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PCI_DEVICE_HEADER_TYPE_REGION Device;
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} PCI_TYPE0_DEVICE, *PPCI_TYPE0_DEVICE;
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/* PCI device type 1 structure */
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typedef struct _PCI_TYPE1_DEVICE
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{
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PCI_DEVICE_INDEPENDENT_REGION Hdr;
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PCI_BRIDGE_CONTROL_REGISTER Bridge;
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} PCI_TYPE1_DEVICE, *PPCI_TYPE1_DEVICE;
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#endif /* __XTDK_IOTYPES_H */
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#endif /* __XTDK_IOTYPES_H */
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