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Rename architecture CPU functions class
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This commit is contained in:
Aiken Harris
2026-05-19 06:45:48 +02:00
parent b03cca65d8
commit 19092eda2e
32 changed files with 271 additions and 270 deletions
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76
xtoskrnl/ar/amd64/cpufunc.cc
View File

@@ -18,7 +18,7 @@
*/
XTCDECL
VOID
AR::CpuFunc::ClearInterruptFlag(VOID)
AR::CpuFunctions::ClearInterruptFlag(VOID)
{
__asm__ volatile("cli");
}
@@ -35,7 +35,7 @@ AR::CpuFunc::ClearInterruptFlag(VOID)
*/
XTCDECL
BOOLEAN
AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
AR::CpuFunctions::CpuId(IN OUT PCPUID_REGISTERS Registers)
{
UINT32 MaxLeaf;
@@ -76,7 +76,7 @@ AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
*/
XTCDECL
VOID
AR::CpuFunc::FlushTlb(VOID)
AR::CpuFunctions::FlushTlb(VOID)
{
/* Flush the TLB by resetting the CR3 */
WriteControlRegister(3, ReadControlRegister(3));
@@ -91,7 +91,7 @@ AR::CpuFunc::FlushTlb(VOID)
*/
XTCDECL
ULONG
AR::CpuFunc::GetCpuFlags(VOID)
AR::CpuFunctions::GetCpuFlags(VOID)
{
ULONG_PTR Flags;
@@ -116,7 +116,7 @@ AR::CpuFunc::GetCpuFlags(VOID)
XTASSEMBLY
XTCDECL
ULONG_PTR
AR::CpuFunc::GetStackPointer(VOID)
AR::CpuFunctions::GetStackPointer(VOID)
{
/* Get current stack pointer */
__asm__ volatile("movq %%rsp, %%rax\n"
@@ -135,7 +135,7 @@ AR::CpuFunc::GetStackPointer(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::Halt(VOID)
AR::CpuFunctions::Halt(VOID)
{
__asm__ volatile("hlt");
}
@@ -149,7 +149,7 @@ AR::CpuFunc::Halt(VOID)
*/
XTCDECL
BOOLEAN
AR::CpuFunc::InterruptsEnabled(VOID)
AR::CpuFunctions::InterruptsEnabled(VOID)
{
ULONG_PTR Flags;
@@ -172,7 +172,7 @@ AR::CpuFunc::InterruptsEnabled(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::InvalidateTlbEntry(IN PVOID Address)
AR::CpuFunctions::InvalidateTlbEntry(IN PVOID Address)
{
__asm__ volatile("invlpg (%0)"
:
@@ -192,7 +192,7 @@ AR::CpuFunc::InvalidateTlbEntry(IN PVOID Address)
*/
XTCDECL
VOID
AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
AR::CpuFunctions::LoadGlobalDescriptorTable(IN PVOID Source)
{
__asm__ volatile("lgdt %0"
:
@@ -212,7 +212,7 @@ AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
*/
XTCDECL
VOID
AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
AR::CpuFunctions::LoadInterruptDescriptorTable(IN PVOID Source)
{
__asm__ volatile("lidt %0"
:
@@ -232,7 +232,7 @@ AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
*/
XTCDECL
VOID
AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
AR::CpuFunctions::LoadLocalDescriptorTable(IN USHORT Source)
{
__asm__ volatile("lldtw %0"
:
@@ -251,7 +251,7 @@ AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
*/
XTCDECL
VOID
AR::CpuFunc::LoadMxcsrRegister(IN ULONG Source)
AR::CpuFunctions::LoadMxcsrRegister(IN ULONG Source)
{
__asm__ volatile("ldmxcsr %0"
:
@@ -273,7 +273,7 @@ AR::CpuFunc::LoadMxcsrRegister(IN ULONG Source)
*/
XTCDECL
VOID
AR::CpuFunc::LoadSegment(IN USHORT Segment,
AR::CpuFunctions::LoadSegment(IN USHORT Segment,
IN ULONG Source)
{
switch(Segment)
@@ -335,7 +335,7 @@ AR::CpuFunc::LoadSegment(IN USHORT Segment,
*/
XTCDECL
VOID
AR::CpuFunc::LoadTaskRegister(USHORT Source)
AR::CpuFunctions::LoadTaskRegister(USHORT Source)
{
__asm__ volatile("ltr %0"
:
@@ -351,7 +351,7 @@ AR::CpuFunc::LoadTaskRegister(USHORT Source)
*/
XTCDECL
VOID
AR::CpuFunc::MemoryBarrier(VOID)
AR::CpuFunctions::MemoryBarrier(VOID)
{
LONG Barrier;
__asm__ volatile("lock; orl $0, %0;"
@@ -371,7 +371,7 @@ AR::CpuFunc::MemoryBarrier(VOID)
*/
XTCDECL
ULONG_PTR
AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
AR::CpuFunctions::ReadControlRegister(IN USHORT ControlRegister)
{
ULONG_PTR Value;
@@ -435,7 +435,7 @@ AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
*/
XTCDECL
ULONG_PTR
AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
AR::CpuFunctions::ReadDebugRegister(IN USHORT DebugRegister)
{
ULONG_PTR Value;
@@ -504,7 +504,7 @@ AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
*/
XTCDECL
ULONGLONG
AR::CpuFunc::ReadGSQuadWord(ULONG Offset)
AR::CpuFunctions::ReadGSQuadWord(ULONG Offset)
{
ULONGLONG Value;
@@ -527,7 +527,7 @@ AR::CpuFunc::ReadGSQuadWord(ULONG Offset)
*/
XTCDECL
ULONGLONG
AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
AR::CpuFunctions::ReadModelSpecificRegister(IN ULONG Register)
{
ULONG Low, High;
@@ -548,7 +548,7 @@ AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
*/
XTCDECL
UINT
AR::CpuFunc::ReadMxCsrRegister(VOID)
AR::CpuFunctions::ReadMxCsrRegister(VOID)
{
return __builtin_ia32_stmxcsr();
}
@@ -562,7 +562,7 @@ AR::CpuFunc::ReadMxCsrRegister(VOID)
*/
XTCDECL
ULONGLONG
AR::CpuFunc::ReadTimeStampCounter(VOID)
AR::CpuFunctions::ReadTimeStampCounter(VOID)
{
ULONGLONG Low, High;
@@ -585,7 +585,7 @@ AR::CpuFunc::ReadTimeStampCounter(VOID)
*/
XTCDECL
ULONGLONG
AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
AR::CpuFunctions::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
{
ULONG Low, High;
@@ -609,7 +609,7 @@ AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
*/
XTCDECL
VOID
AR::CpuFunc::ReadWriteBarrier(VOID)
AR::CpuFunctions::ReadWriteBarrier(VOID)
{
__asm__ volatile(""
:
@@ -626,7 +626,7 @@ AR::CpuFunc::ReadWriteBarrier(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::SetInterruptFlag(VOID)
AR::CpuFunctions::SetInterruptFlag(VOID)
{
__asm__ volatile("sti");
}
@@ -643,7 +643,7 @@ AR::CpuFunc::SetInterruptFlag(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
AR::CpuFunctions::StoreGlobalDescriptorTable(OUT PVOID Destination)
{
__asm__ volatile("sgdt %0"
: "=m" (*(PSHORT)Destination)
@@ -663,7 +663,7 @@ AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
AR::CpuFunctions::StoreInterruptDescriptorTable(OUT PVOID Destination)
{
__asm__ volatile("sidt %0"
: "=m" (*(PSHORT)Destination)
@@ -683,7 +683,7 @@ AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
AR::CpuFunctions::StoreLocalDescriptorTable(OUT PVOID Destination)
{
__asm__ volatile("sldt %0"
: "=m" (*(PSHORT)Destination)
@@ -706,8 +706,8 @@ AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::StoreSegment(IN USHORT Segment,
OUT PVOID Destination)
AR::CpuFunctions::StoreSegment(IN USHORT Segment,
OUT PVOID Destination)
{
switch(Segment)
{
@@ -753,7 +753,7 @@ AR::CpuFunc::StoreSegment(IN USHORT Segment,
*/
XTCDECL
VOID
AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
AR::CpuFunctions::StoreTaskRegister(OUT PVOID Destination)
{
__asm__ volatile("str %0"
: "=m" (*(PULONG)Destination)
@@ -776,8 +776,8 @@ AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
IN UINT_PTR Value)
AR::CpuFunctions::WriteControlRegister(IN USHORT ControlRegister,
IN UINT_PTR Value)
{
/* Write a value into specified control register */
switch(ControlRegister)
@@ -835,8 +835,8 @@ AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
*/
XTCDECL
VOID
AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
IN UINT_PTR Value)
AR::CpuFunctions::WriteDebugRegister(IN USHORT DebugRegister,
IN UINT_PTR Value)
{
/* Write a value into specified debug register */
switch(DebugRegister)
@@ -912,7 +912,7 @@ AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
*/
XTCDECL
VOID
AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
AR::CpuFunctions::WriteEflagsRegister(IN UINT_PTR Value)
{
__asm__ volatile("push %0\n"
"popf"
@@ -935,8 +935,8 @@ AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
*/
XTCDECL
VOID
AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value)
AR::CpuFunctions::WriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value)
{
ULONG Low = Value & 0xFFFFFFFF;
ULONG High = Value >> 32;
@@ -957,7 +957,7 @@ AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
*/
XTCDECL
VOID
AR::CpuFunc::YieldProcessor(VOID)
AR::CpuFunctions::YieldProcessor(VOID)
{
__asm__ volatile("pause"
:

65
xtoskrnl/ar/amd64/procsup.cc
View File

@@ -75,7 +75,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
/* Get CPU vendor by issueing CPUID instruction */
RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU vendor in processor control block */
Prcb->CpuId.Vendor = (CPU_VENDOR)CpuRegisters.Ebx;
@@ -87,7 +87,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
/* Get CPU standard features */
RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU signature in processor control block */
CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
@@ -149,13 +149,13 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get maximum CPUID standard leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
MaxStandardLeaf = CpuRegisters.Eax;
/* Get maximum CPUID extended leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_EXTENDED_MAX;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
MaxExtendedLeaf = CpuRegisters.Eax;
/* Check if CPU supports standard features leaf */
@@ -164,7 +164,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU standard features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU standard features in processor control block */
if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SSE3) Prcb->CpuId.FeatureBits |= KCF_SSE3;
@@ -208,7 +208,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU standard features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_STANDARD7_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU standard7 features in processor control block */
if(CpuRegisters.Ebx & CPUID_FEATURES_EBX_FSGSBASE) Prcb->CpuId.FeatureBits |= KCF_FSGSBASE;
@@ -226,7 +226,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU power management features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_POWER_MANAGEMENT;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU power management features in processor control block */
if(CpuRegisters.Eax & CPUID_FEATURES_EAX_ARAT) Prcb->CpuId.FeatureBits |= KCF_ARAT;
@@ -238,7 +238,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU extended features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_EXTENDED_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU extended features in processor control block */
if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SVM) Prcb->CpuId.ExtendedFeatureBits |= KCF_SVM;
@@ -259,7 +259,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU advanced power management features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_ADVANCED_POWER_MANAGEMENT;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU advanced power management features in processor control block */
if(CpuRegisters.Edx & CPUID_FEATURES_EDX_TSCI) Prcb->CpuId.ExtendedFeatureBits |= KCF_INVARIANT_TSC;
@@ -401,16 +401,16 @@ AR::ProcessorSupport::InitializeProcessor(IN PVOID ProcessorStructures)
IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
/* Load GDT, IDT and TSS */
AR::CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
AR::CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
AR::CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
AR::CpuFunctions::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
AR::CpuFunctions::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
AR::CpuFunctions::LoadTaskRegister((UINT)KGDT_SYS_TSS);
/* Initialize segment registers */
InitializeSegments();
/* Set GS base */
AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
/* Initialize processor registers */
InitializeProcessorRegisters();
@@ -495,45 +495,46 @@ AR::ProcessorSupport::InitializeProcessorRegisters(VOID)
ULONGLONG PatAttributes;
/* Enable FXSAVE restore */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_FXSR);
AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_FXSR);
/* Enable XMMI exceptions */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_XMMEXCPT);
AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_XMMEXCPT);
/* Set debugger extension */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_DE);
AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_DE);
/* Enable large pages */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PSE);
AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_PSE);
/* Enable write-protection */
AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_WP);
AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) | CR0_WP);
/* Set alignment mask */
AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_AM);
AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) | CR0_AM);
/* Disable FPU monitoring */
AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) & ~CR0_MP);
AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) & ~CR0_MP);
/* Disable x87 FPU exceptions */
AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) & ~CR0_NE);
AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) & ~CR0_NE);
/* Flush the TLB */
AR::CpuFunc::FlushTlb();
AR::CpuFunctions::FlushTlb();
/* Initialize system call MSRs */
AR::Traps::InitializeSystemCallMsrs();
/* Enable No-Execute (NXE) in EFER MSR */
AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunc::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_EFER,
CpuFunctions::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
/* Initialize Page Attribute Table */
PatAttributes = (PAT_TYPE_WB << 0) | (PAT_TYPE_USWC << 8) | (PAT_TYPE_WEAK_UC << 16) | (PAT_TYPE_STRONG_UC << 24) |
(PAT_TYPE_WB << 32) | (PAT_TYPE_USWC << 40) | (PAT_TYPE_WEAK_UC << 48) | (PAT_TYPE_STRONG_UC << 56);
AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
/* Initialize MXCSR register */
AR::CpuFunc::LoadMxcsrRegister(INITIAL_MXCSR);
AR::CpuFunctions::LoadMxcsrRegister(INITIAL_MXCSR);
}
/**
@@ -634,12 +635,12 @@ VOID
AR::ProcessorSupport::InitializeSegments(VOID)
{
/* Initialize segments */
AR::CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
AR::CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R3_CMTEB | RPL_MASK);
AR::CpuFunc::LoadSegment(SEGMENT_GS, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
AR::CpuFunctions::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
AR::CpuFunctions::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunctions::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunctions::LoadSegment(SEGMENT_FS, KGDT_R3_CMTEB | RPL_MASK);
AR::CpuFunctions::LoadSegment(SEGMENT_GS, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunctions::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
}
/**

14
xtoskrnl/ar/amd64/traps.cc
View File

@@ -26,8 +26,8 @@ AR::Traps::DispatchInterrupt(IN PKTRAP_FRAME TrapFrame)
PINTERRUPT_HANDLER Handler;
/* Read the handler pointer from the CPU's interrupt dispatch table */
Handler = (PINTERRUPT_HANDLER)AR::CpuFunc::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
(TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
Handler = (PINTERRUPT_HANDLER)AR::CpuFunctions::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
(TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
/* Check if the interrupt has a handler registered */
if(Handler != NULLPTR)
@@ -672,13 +672,13 @@ VOID
AR::Traps::InitializeSystemCallMsrs(VOID)
{
/* Initialize system calls MSR */
CpuFunc::WriteModelSpecificRegister(X86_MSR_STAR, (((ULONG64)KGDT_R3_CMCODE | RPL_MASK) << 48) | ((ULONG64)KGDT_R0_CODE << 32));
CpuFunc::WriteModelSpecificRegister(X86_MSR_CSTAR, (ULONG64)&HandleSystemCall32);
CpuFunc::WriteModelSpecificRegister(X86_MSR_LSTAR, (ULONG64)&HandleSystemCall64);
CpuFunc::WriteModelSpecificRegister(X86_MSR_FMASK, X86_EFLAGS_IF_MASK | X86_EFLAGS_TF_MASK);
CpuFunctions::WriteModelSpecificRegister(X86_MSR_STAR, (((ULONG64)KGDT_R3_CMCODE | RPL_MASK) << 48) | ((ULONG64)KGDT_R0_CODE << 32));
CpuFunctions::WriteModelSpecificRegister(X86_MSR_CSTAR, (ULONG64)&HandleSystemCall32);
CpuFunctions::WriteModelSpecificRegister(X86_MSR_LSTAR, (ULONG64)&HandleSystemCall64);
CpuFunctions::WriteModelSpecificRegister(X86_MSR_FMASK, X86_EFLAGS_IF_MASK | X86_EFLAGS_TF_MASK);
/* Enable system call extensions (SCE) in EFER MSR */
CpuFunc::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunc::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
CpuFunctions::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunctions::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
}
/**

76
xtoskrnl/ar/i686/cpufunc.cc
View File

@@ -18,7 +18,7 @@
*/
XTCDECL
VOID
AR::CpuFunc::ClearInterruptFlag(VOID)
AR::CpuFunctions::ClearInterruptFlag(VOID)
{
__asm__ volatile("cli");
}
@@ -35,7 +35,7 @@ AR::CpuFunc::ClearInterruptFlag(VOID)
*/
XTCDECL
BOOLEAN
AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
AR::CpuFunctions::CpuId(IN OUT PCPUID_REGISTERS Registers)
{
UINT32 MaxLeaf;
@@ -76,7 +76,7 @@ AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
*/
XTCDECL
VOID
AR::CpuFunc::FlushTlb(VOID)
AR::CpuFunctions::FlushTlb(VOID)
{
/* Flush the TLB by resetting the CR3 */
WriteControlRegister(3, ReadControlRegister(3));
@@ -91,7 +91,7 @@ AR::CpuFunc::FlushTlb(VOID)
*/
XTCDECL
ULONG
AR::CpuFunc::GetCpuFlags(VOID)
AR::CpuFunctions::GetCpuFlags(VOID)
{
ULONG_PTR Flags;
@@ -116,7 +116,7 @@ AR::CpuFunc::GetCpuFlags(VOID)
XTASSEMBLY
XTCDECL
ULONG_PTR
AR::CpuFunc::GetStackPointer(VOID)
AR::CpuFunctions::GetStackPointer(VOID)
{
/* Get current stack pointer */
__asm__ volatile("mov %%esp, %%eax\n"
@@ -135,7 +135,7 @@ AR::CpuFunc::GetStackPointer(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::Halt(VOID)
AR::CpuFunctions::Halt(VOID)
{
__asm__ volatile("hlt");
}
@@ -149,7 +149,7 @@ AR::CpuFunc::Halt(VOID)
*/
XTCDECL
BOOLEAN
AR::CpuFunc::InterruptsEnabled(VOID)
AR::CpuFunctions::InterruptsEnabled(VOID)
{
ULONG_PTR Flags;
@@ -172,7 +172,7 @@ AR::CpuFunc::InterruptsEnabled(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::InvalidateTlbEntry(PVOID Address)
AR::CpuFunctions::InvalidateTlbEntry(PVOID Address)
{
__asm__ volatile("invlpg (%0)"
:
@@ -192,7 +192,7 @@ AR::CpuFunc::InvalidateTlbEntry(PVOID Address)
*/
XTCDECL
VOID
AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
AR::CpuFunctions::LoadGlobalDescriptorTable(IN PVOID Source)
{
__asm__ volatile("lgdt %0"
:
@@ -212,7 +212,7 @@ AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
*/
XTCDECL
VOID
AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
AR::CpuFunctions::LoadInterruptDescriptorTable(IN PVOID Source)
{
__asm__ volatile("lidt %0"
:
@@ -232,7 +232,7 @@ AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
*/
XTCDECL
VOID
AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
AR::CpuFunctions::LoadLocalDescriptorTable(IN USHORT Source)
{
__asm__ volatile("lldtw %0"
:
@@ -254,8 +254,8 @@ AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
*/
XTCDECL
VOID
AR::CpuFunc::LoadSegment(IN USHORT Segment,
IN ULONG Source)
AR::CpuFunctions::LoadSegment(IN USHORT Segment,
IN ULONG Source)
{
switch(Segment)
{
@@ -316,7 +316,7 @@ AR::CpuFunc::LoadSegment(IN USHORT Segment,
*/
XTCDECL
VOID
AR::CpuFunc::LoadTaskRegister(USHORT Source)
AR::CpuFunctions::LoadTaskRegister(USHORT Source)
{
__asm__ volatile("ltr %0"
:
@@ -332,7 +332,7 @@ AR::CpuFunc::LoadTaskRegister(USHORT Source)
*/
XTCDECL
VOID
AR::CpuFunc::MemoryBarrier(VOID)
AR::CpuFunctions::MemoryBarrier(VOID)
{
LONG Barrier;
__asm__ volatile("xchg %%eax, %0"
@@ -353,7 +353,7 @@ AR::CpuFunc::MemoryBarrier(VOID)
*/
XTCDECL
ULONG_PTR
AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
AR::CpuFunctions::ReadControlRegister(IN USHORT ControlRegister)
{
ULONG_PTR Value;
@@ -410,7 +410,7 @@ AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
*/
XTCDECL
ULONG_PTR
AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
AR::CpuFunctions::ReadDebugRegister(IN USHORT DebugRegister)
{
ULONG_PTR Value;
@@ -479,7 +479,7 @@ AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
*/
XTCDECL
ULONG
AR::CpuFunc::ReadFSDualWord(ULONG Offset)
AR::CpuFunctions::ReadFSDualWord(ULONG Offset)
{
ULONG Value;
__asm__ volatile("movl %%fs:%a[Offset], %k[Value]"
@@ -500,7 +500,7 @@ AR::CpuFunc::ReadFSDualWord(ULONG Offset)
*/
XTCDECL
ULONGLONG
AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
AR::CpuFunctions::ReadModelSpecificRegister(IN ULONG Register)
{
ULONGLONG Value;
@@ -519,7 +519,7 @@ AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
*/
XTCDECL
UINT
AR::CpuFunc::ReadMxCsrRegister(VOID)
AR::CpuFunctions::ReadMxCsrRegister(VOID)
{
return __builtin_ia32_stmxcsr();
}
@@ -533,7 +533,7 @@ AR::CpuFunc::ReadMxCsrRegister(VOID)
*/
XTCDECL
ULONGLONG
AR::CpuFunc::ReadTimeStampCounter(VOID)
AR::CpuFunctions::ReadTimeStampCounter(VOID)
{
ULONGLONG Value;
@@ -555,7 +555,7 @@ AR::CpuFunc::ReadTimeStampCounter(VOID)
*/
XTCDECL
ULONGLONG
AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
AR::CpuFunctions::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
{
ULONG Low, High;
@@ -579,7 +579,7 @@ AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
*/
XTCDECL
VOID
AR::CpuFunc::ReadWriteBarrier(VOID)
AR::CpuFunctions::ReadWriteBarrier(VOID)
{
__asm__ volatile(""
:
@@ -596,7 +596,7 @@ AR::CpuFunc::ReadWriteBarrier(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::SetInterruptFlag(VOID)
AR::CpuFunctions::SetInterruptFlag(VOID)
{
__asm__ volatile("sti");
}
@@ -613,7 +613,7 @@ AR::CpuFunc::SetInterruptFlag(VOID)
*/
XTCDECL
VOID
AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
AR::CpuFunctions::StoreGlobalDescriptorTable(OUT PVOID Destination)
{
__asm__ volatile("sgdt %0"
: "=m" (*(PSHORT)Destination)
@@ -633,7 +633,7 @@ AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
AR::CpuFunctions::StoreInterruptDescriptorTable(OUT PVOID Destination)
{
__asm__ volatile("sidt %0"
: "=m" (*(PSHORT)Destination)
@@ -653,7 +653,7 @@ AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
AR::CpuFunctions::StoreLocalDescriptorTable(OUT PVOID Destination)
{
__asm__ volatile("sldt %0"
: "=m" (*(PSHORT)Destination)
@@ -676,8 +676,8 @@ AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::StoreSegment(IN USHORT Segment,
OUT PVOID Destination)
AR::CpuFunctions::StoreSegment(IN USHORT Segment,
OUT PVOID Destination)
{
switch(Segment)
{
@@ -723,7 +723,7 @@ AR::CpuFunc::StoreSegment(IN USHORT Segment,
*/
XTCDECL
VOID
AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
AR::CpuFunctions::StoreTaskRegister(OUT PVOID Destination)
{
__asm__ volatile("str %0"
: "=m" (*(PULONG)Destination)
@@ -746,8 +746,8 @@ AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
*/
XTCDECL
VOID
AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
IN UINT_PTR Value)
AR::CpuFunctions::WriteControlRegister(IN USHORT ControlRegister,
IN UINT_PTR Value)
{
/* Write a value into specified control register */
switch(ControlRegister)
@@ -798,8 +798,8 @@ AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
*/
XTCDECL
VOID
AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
IN UINT_PTR Value)
AR::CpuFunctions::WriteDebugRegister(IN USHORT DebugRegister,
IN UINT_PTR Value)
{
/* Write a value into specified debug register */
switch(DebugRegister)
@@ -867,7 +867,7 @@ AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
*/
XTCDECL
VOID
AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
AR::CpuFunctions::WriteEflagsRegister(IN UINT_PTR Value)
{
__asm__ volatile("push %0\n"
"popf"
@@ -890,8 +890,8 @@ AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
*/
XTCDECL
VOID
AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value)
AR::CpuFunctions::WriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value)
{
__asm__ volatile("wrmsr"
:
@@ -908,7 +908,7 @@ AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
*/
XTCDECL
VOID
AR::CpuFunc::YieldProcessor(VOID)
AR::CpuFunctions::YieldProcessor(VOID)
{
__asm__ volatile("pause"
:

46
xtoskrnl/ar/i686/procsup.cc
View File

@@ -68,7 +68,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
/* Get CPU vendor by issueing CPUID instruction */
RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU vendor in processor control block */
Prcb->CpuId.Vendor = (CPU_VENDOR)CpuRegisters.Ebx;
@@ -80,7 +80,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
/* Get CPU standard features */
RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU signature in processor control block */
CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
@@ -142,13 +142,13 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get maximum CPUID standard leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
MaxStandardLeaf = CpuRegisters.Eax;
/* Get maximum CPUID extended leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_EXTENDED_MAX;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
MaxExtendedLeaf = CpuRegisters.Eax;
/* Check if CPU supports standard features leaf */
@@ -157,7 +157,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU standard features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU standard features in processor control block */
if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SSE3) Prcb->CpuId.FeatureBits |= KCF_SSE3;
@@ -201,7 +201,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU standard features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_STANDARD7_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU standard7 features in processor control block */
if(CpuRegisters.Ebx & CPUID_FEATURES_EBX_FSGSBASE) Prcb->CpuId.FeatureBits |= KCF_FSGSBASE;
@@ -219,7 +219,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU power management features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_POWER_MANAGEMENT;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU power management features in processor control block */
if(CpuRegisters.Eax & CPUID_FEATURES_EAX_ARAT) Prcb->CpuId.FeatureBits |= KCF_ARAT;
@@ -231,7 +231,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU extended features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_EXTENDED_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU extended features in processor control block */
if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SVM) Prcb->CpuId.ExtendedFeatureBits |= KCF_SVM;
@@ -252,7 +252,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
/* Get CPU advanced power management features */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_ADVANCED_POWER_MANAGEMENT;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Store CPU advanced power management features in processor control block */
if(CpuRegisters.Edx & CPUID_FEATURES_EDX_TSCI) Prcb->CpuId.ExtendedFeatureBits |= KCF_INVARIANT_TSC;
@@ -397,9 +397,9 @@ AR::ProcessorSupport::InitializeProcessor(IN PVOID ProcessorStructures)
IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
/* Load GDT, IDT and TSS */
AR::CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
AR::CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
AR::CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
AR::CpuFunctions::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
AR::CpuFunctions::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
AR::CpuFunctions::LoadTaskRegister((UINT)KGDT_SYS_TSS);
/* Initialize segment registers */
InitializeSegments();
@@ -481,10 +481,10 @@ VOID
AR::ProcessorSupport::InitializeProcessorRegisters(VOID)
{
/* Clear EFLAGS register */
AR::CpuFunc::WriteEflagsRegister(0);
AR::CpuFunctions::WriteEflagsRegister(0);
/* Enable write-protection */
AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_WP);
AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) | CR0_WP);
}
/**
@@ -585,12 +585,12 @@ VOID
AR::ProcessorSupport::InitializeSegments(VOID)
{
/* Initialize segments */
AR::CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
AR::CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R0_PB);
AR::CpuFunc::LoadSegment(SEGMENT_GS, 0);
AR::CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
AR::CpuFunctions::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
AR::CpuFunctions::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunctions::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
AR::CpuFunctions::LoadSegment(SEGMENT_FS, KGDT_R0_PB);
AR::CpuFunctions::LoadSegment(SEGMENT_GS, 0);
AR::CpuFunctions::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
}
/**
@@ -644,7 +644,7 @@ AR::ProcessorSupport::InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
ProcessorBlock->TssBase->Flags = 0;
/* Set CR3, LDT and SS */
ProcessorBlock->TssBase->CR3 = AR::CpuFunc::ReadControlRegister(3);
ProcessorBlock->TssBase->CR3 = AR::CpuFunctions::ReadControlRegister(3);
ProcessorBlock->TssBase->LDT = 0;
ProcessorBlock->TssBase->Ss0 = KGDT_R0_DATA;
@@ -683,7 +683,7 @@ AR::ProcessorSupport::SetDoubleFaultTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock
Tss->IoMapBase = sizeof(KTSS);
Tss->Flags = 0;
Tss->LDT = 0;
Tss->CR3 = AR::CpuFunc::ReadControlRegister(3);
Tss->CR3 = AR::CpuFunctions::ReadControlRegister(3);
Tss->Esp = (ULONG_PTR)KernelFaultStack;
Tss->Esp0 = (ULONG_PTR)KernelFaultStack;
Tss->Eip = (ULONG)(ULONG_PTR)ArTrapEntry[0x08];
@@ -897,7 +897,7 @@ AR::ProcessorSupport::SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK Proce
Tss->IoMapBase = sizeof(KTSS);
Tss->Flags = 0;
Tss->LDT = 0;
Tss->CR3 = AR::CpuFunc::ReadControlRegister(3);
Tss->CR3 = AR::CpuFunctions::ReadControlRegister(3);
Tss->Esp = (ULONG_PTR)KernelNmiStack;
Tss->Esp0 = (ULONG_PTR)KernelNmiStack;
Tss->Eip = (ULONG)(ULONG_PTR)ArTrapEntry[0x02];

4
xtoskrnl/ar/i686/traps.cc
View File

@@ -26,8 +26,8 @@ AR::Traps::DispatchInterrupt(IN PKTRAP_FRAME TrapFrame)
PINTERRUPT_HANDLER Handler;
/* Read the handler pointer from the CPU's interrupt dispatch table */
Handler = (PINTERRUPT_HANDLER)AR::CpuFunc::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
(TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
Handler = (PINTERRUPT_HANDLER)AR::CpuFunctions::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
(TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
/* Check if the interrupt has a handler registered */
if(Handler != NULLPTR)

6
xtoskrnl/hl/amd64/irq.cc
View File

@@ -36,7 +36,7 @@ HL::Irq::BeginSystemInterrupt(IN KRUNLEVEL RunLevel,
KE::RunLevel::RaiseRunLevel(RunLevel);
/* Enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/**
@@ -58,7 +58,7 @@ HL::Irq::EndInterrupt(IN PKTRAP_FRAME TrapFrame,
IN KRUNLEVEL OldRunLevel)
{
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* End system interrupt */
EndSystemInterrupt(TrapFrame, OldRunLevel);
@@ -125,7 +125,7 @@ HL::Irq::HandleUnexpectedInterrupt(IN PKTRAP_FRAME TrapFrame)
UNIMPLEMENTED;
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Print debug message and raise kernel panic */
DebugPrint(L"ERROR: Caught unexpected interrupt (0x%.2llX)!\n", TrapFrame->Vector);

4
xtoskrnl/hl/amd64/runlevel.cc
View File

@@ -21,7 +21,7 @@ KRUNLEVEL
HL::RunLevel::GetRunLevel(VOID)
{
/* Read current run level */
return (KRUNLEVEL)AR::CpuFunc::ReadControlRegister(8);
return (KRUNLEVEL)AR::CpuFunctions::ReadControlRegister(8);
}
/**
@@ -39,7 +39,7 @@ VOID
HL::RunLevel::SetRunLevel(IN KRUNLEVEL RunLevel)
{
/* Set new run level */
AR::CpuFunc::WriteControlRegister(8, RunLevel);
AR::CpuFunctions::WriteControlRegister(8, RunLevel);
}
/**

6
xtoskrnl/hl/i686/irq.cc
View File

@@ -37,7 +37,7 @@ HL::Irq::BeginSystemInterrupt(IN KRUNLEVEL RunLevel,
KE::RunLevel::RaiseRunLevel(RunLevel);
/* Enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/**
@@ -59,7 +59,7 @@ HL::Irq::EndInterrupt(IN PKTRAP_FRAME TrapFrame,
IN KRUNLEVEL OldRunLevel)
{
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* End system interrupt */
EndSystemInterrupt(TrapFrame, OldRunLevel);
@@ -126,7 +126,7 @@ HL::Irq::HandleUnexpectedInterrupt(IN PKTRAP_FRAME TrapFrame)
UNIMPLEMENTED;
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Print debug message and raise kernel panic */
DebugPrint(L"ERROR: Caught unexpected interrupt (0x%.2lX)!\n", TrapFrame->Vector);

8
xtoskrnl/hl/x86/cpu.cc
View File

@@ -171,14 +171,14 @@ HL::Cpu::StartAllProcessors(VOID)
KE::Processor::RegisterProcessorBlock(CpuNumber, ProcessorBlock);
/* Initialize processor start block */
StartBlock->Cr3 = AR::CpuFunc::ReadControlRegister(3);
StartBlock->Cr4 = AR::CpuFunc::ReadControlRegister(4);
StartBlock->Cr3 = AR::CpuFunctions::ReadControlRegister(3);
StartBlock->Cr4 = AR::CpuFunctions::ReadControlRegister(4);
StartBlock->EntryPoint = (PVOID)&KE::KernelInit::BootstrapApplicationProcessor;
StartBlock->ProcessorStructures = CpuStructures;
StartBlock->Started = FALSE;
/* Memory barrier */
AR::CpuFunc::MemoryBarrier();
AR::CpuFunctions::MemoryBarrier();
/* Send INIT IPI and wait for 10ms */
HL::Pic::SendIpi(SysInfo->CpuInfo[Index].ApicId, 0, APIC_DM_INIT, APIC_DSH_Destination, APIC_TGM_EDGE);
@@ -196,7 +196,7 @@ HL::Cpu::StartAllProcessors(VOID)
while(!StartBlock->Started && Timeout < 100000)
{
/* Yield processor and wait for 10us */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
HL::Timer::StallExecution(10);
Timeout++;
}

30
xtoskrnl/hl/x86/pic.cc
View File

@@ -364,11 +364,11 @@ HL::Pic::InitializeApic(VOID)
CpuNumber = KE::Processor::GetCurrentProcessorNumber();
/* Enable the APIC */
BaseRegister.LongLong = AR::CpuFunc::ReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
BaseRegister.LongLong = AR::CpuFunctions::ReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
BaseRegister.Enable = 1;
BaseRegister.ExtendedMode = (ApicMode == APIC_MODE_X2APIC);
BaseRegister.BootStrapProcessor = (CpuNumber == 0) ? 1 : 0;
AR::CpuFunc::WriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
AR::CpuFunctions::WriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
/* Mask all interrupts by raising Task Priority Register (TPR) */
WriteApicRegister(APIC_TPR, 0xFF);
@@ -479,8 +479,8 @@ HL::Pic::InitializeIOApic(VOID)
}
/* Perform a memory barrier */
AR::CpuFunc::MemoryBarrier();
AR::CpuFunc::ReadWriteBarrier();
AR::CpuFunctions::MemoryBarrier();
AR::CpuFunctions::ReadWriteBarrier();
/* Read the version register and calculate the maximum number of redirection entries */
VersionRegister = ReadIOApicRegister(&Controllers[ControllerIndex], IOAPIC_VER);
@@ -639,7 +639,7 @@ HL::Pic::ReadApicRegister(IN APIC_REGISTER Register)
if(ApicMode == APIC_MODE_X2APIC)
{
/* Read from x2APIC MSR */
return AR::CpuFunc::ReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
return AR::CpuFunctions::ReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
}
else
{
@@ -782,10 +782,10 @@ HL::Pic::SendBroadcastIpi(IN ULONG Vector,
HL::Acpi::GetSystemInformation(&SysInfo);
/* Check whether interrupts are enabled */
Interrupts = AR::CpuFunc::InterruptsEnabled();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Iterate over all logical CPUs */
for(Index = 0; Index < SysInfo->CpuCount; Index++)
@@ -818,7 +818,7 @@ HL::Pic::SendBroadcastIpi(IN ULONG Vector,
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
}
@@ -871,10 +871,10 @@ HL::Pic::SendIpi(IN ULONG ApicId,
BOOLEAN Interrupts;
/* Check whether interrupts are enabled */
Interrupts = AR::CpuFunc::InterruptsEnabled();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Check current APIC mode and destination */
if(ApicMode == APIC_MODE_X2APIC && DestinationShortHand == APIC_DSH_Self)
@@ -886,7 +886,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
if(Interrupts)
{
/* Check whether interrupts need to be re-enabled */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/* Nothing more to do */
@@ -917,7 +917,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
while((ReadApicRegister(APIC_ICR0) & 0x1000) != 0)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
/* In xAPIC compatibility mode, write the command to the ICR registers */
@@ -931,7 +931,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
while((ReadApicRegister((APIC_REGISTER)(APIC_IRR + (Vector / 32))) & (1UL << (Vector % 32))) == 0)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}
}
@@ -940,7 +940,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
}
@@ -1016,7 +1016,7 @@ HL::Pic::WriteApicRegister(IN APIC_REGISTER Register,
if(ApicMode == APIC_MODE_X2APIC)
{
/* Write to x2APIC MSR */
AR::CpuFunc::WriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
AR::CpuFunctions::WriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
}
else
{

4
xtoskrnl/hl/x86/rtc.cc
View File

@@ -58,7 +58,7 @@ HL::Rtc::GetRealTimeClock(OUT PTIME_FIELDS Time)
while(HL::Firmware::ReadCmosRegister(CMOS_REGISTER_A) & CMOS_REGISTER_A_UPDATE_IN_PROGRESS)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
/* Latch the first sequential hardware time snapshot */
@@ -81,7 +81,7 @@ HL::Rtc::GetRealTimeClock(OUT PTIME_FIELDS Time)
while(HL::Firmware::ReadCmosRegister(CMOS_REGISTER_A) & CMOS_REGISTER_A_UPDATE_IN_PROGRESS)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
/* Latch the second sequential hardware time snapshot for verification */

26
xtoskrnl/hl/x86/timer.cc
View File

@@ -84,13 +84,13 @@ HL::Timer::CalibrateTscCounter(VOID)
}
/* Latch the initial TSC value */
InitialTickCount = AR::CpuFunc::ReadTimeStampCounterProcessor(&TscAux);
InitialTickCount = AR::CpuFunctions::ReadTimeStampCounterProcessor(&TscAux);
/* Stall CPU execution for exactly 10 milliseconds */
StallExecution(10000);
/* Read current tick count from TSC */
FinalTickCount = AR::CpuFunc::ReadTimeStampCounterProcessor(&TscAux);
FinalTickCount = AR::CpuFunctions::ReadTimeStampCounterProcessor(&TscAux);
/* Calculate the elapsed ticks over the 10ms window */
return (FinalTickCount - InitialTickCount) * 100;
@@ -915,7 +915,7 @@ HL::Timer::QueryPerformanceCounterTsc(VOID)
ULONG TscAux;
/* Retrieve the timestamp */
return AR::CpuFunc::ReadTimeStampCounterProcessor(&TscAux);
return AR::CpuFunctions::ReadTimeStampCounterProcessor(&TscAux);
}
/**
@@ -945,7 +945,7 @@ HL::Timer::QueryTimerCapabilities(VOID)
/* Query maximum standard CPUID leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
MaxStandardLeaf = CpuRegisters.Eax;
/* Check Always Running Timer - ART if leaf supported */
@@ -954,7 +954,7 @@ HL::Timer::QueryTimerCapabilities(VOID)
/* Query the Time Stamp Counter and Core Crystal Clock information CPUID leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_TSC_CRYSTAL_CLOCK;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Verify Always Running Timer support */
if(CpuRegisters.Eax != 0 && CpuRegisters.Ebx != 0)
@@ -1051,10 +1051,10 @@ HL::Timer::SetClockRateApic(ULONG Rate)
}
/* Check whether interrupts are enabled */
Interrupts = AR::CpuFunc::InterruptsEnabled();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Commit the new divider to the TICR register */
HL::Pic::WriteApicRegister(APIC_TICR, NewDivider);
@@ -1066,7 +1066,7 @@ HL::Timer::SetClockRateApic(ULONG Rate)
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/* Return the actual clock rate set */
@@ -1178,7 +1178,7 @@ HL::Timer::StallExecutionAcpiPm(IN ULONG MicroSeconds)
StartTick = CurrentTick;
/* Issue a PAUSE instruction to relieve memory bus contention */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}
@@ -1222,7 +1222,7 @@ HL::Timer::StallExecutionHpet(IN ULONG MicroSeconds)
while((Hpet->MainCounterValue - StartTick) < TargetTicks)
{
/* Issue a PAUSE instruction to relieve memory bus contention */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}
@@ -1327,13 +1327,13 @@ HL::Timer::StallExecutionTsc(IN ULONG MicroSeconds)
/* Calculate target ticks based on calibrated TSC frequency */
TargetTicks = ((ULONGLONG)MicroSeconds * PerformanceFrequency) / 1000000ULL;
StartTick = AR::CpuFunc::ReadTimeStampCounter();
StartTick = AR::CpuFunctions::ReadTimeStampCounter();
/* Spin until the elapsed ticks reach the target */
while((AR::CpuFunc::ReadTimeStampCounter() - StartTick) < TargetTicks)
while((AR::CpuFunctions::ReadTimeStampCounter() - StartTick) < TargetTicks)
{
/* Issue a PAUSE instruction to relieve memory bus contention */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}

2
xtoskrnl/includes/ar/amd64/cpufunc.hh
View File

@@ -15,7 +15,7 @@
/* Architecture-specific Library */
namespace AR
{
class CpuFunc
class CpuFunctions
{
public:
STATIC XTCDECL VOID ClearInterruptFlag(VOID);

2
xtoskrnl/includes/ar/i686/cpufunc.hh
View File

@@ -15,7 +15,7 @@
/* Architecture-specific Library */
namespace AR
{
class CpuFunc
class CpuFunctions
{
public:
STATIC XTCDECL VOID ClearInterruptFlag(VOID);

54
xtoskrnl/ke/amd64/proc.cc
View File

@@ -21,7 +21,7 @@ PKPROCESSOR_BLOCK
KE::Processor::GetCurrentProcessorBlock(VOID)
{
/* Get processor block from GS register */
return (PKPROCESSOR_BLOCK)AR::CpuFunc::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Self));
return (PKPROCESSOR_BLOCK)AR::CpuFunctions::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Self));
}
/**
@@ -35,7 +35,7 @@ XTAPI
PKPROCESSOR_CONTROL_BLOCK
KE::Processor::GetCurrentProcessorControlBlock(VOID)
{
return (PKPROCESSOR_CONTROL_BLOCK)AR::CpuFunc::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CurrentPrcb));
return (PKPROCESSOR_CONTROL_BLOCK)AR::CpuFunctions::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CurrentPrcb));
}
/**
@@ -49,7 +49,7 @@ XTAPI
ULONG
KE::Processor::GetCurrentProcessorNumber(VOID)
{
return (ULONG)AR::CpuFunc::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CpuNumber));
return (ULONG)AR::CpuFunctions::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CpuNumber));
}
/**
@@ -63,7 +63,7 @@ XTAPI
PKTHREAD
KE::Processor::GetCurrentThread(VOID)
{
return (PKTHREAD)AR::CpuFunc::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Prcb.CurrentThread));
return (PKTHREAD)AR::CpuFunctions::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Prcb.CurrentThread));
}
/**
@@ -158,7 +158,7 @@ KE::Processor::RegisterHardwareId(IN ULONG HardwareId)
* Specifies the logical processor number.
*
* @param ProcessorBlock
* Supplies a pointer to the processor block.
* Supplies a pointer to the processor block.
*
* @return This routine does not return any value.
*
@@ -192,34 +192,34 @@ VOID
KE::Processor::SaveProcessorState(OUT PKPROCESSOR_STATE CpuState)
{
/* Save CR registers */
CpuState->SpecialRegisters.Cr0 = AR::CpuFunc::ReadControlRegister(0);
CpuState->SpecialRegisters.Cr2 = AR::CpuFunc::ReadControlRegister(2);
CpuState->SpecialRegisters.Cr3 = AR::CpuFunc::ReadControlRegister(3);
CpuState->SpecialRegisters.Cr4 = AR::CpuFunc::ReadControlRegister(4);
CpuState->SpecialRegisters.Cr8 = AR::CpuFunc::ReadControlRegister(8);
CpuState->SpecialRegisters.Cr0 = AR::CpuFunctions::ReadControlRegister(0);
CpuState->SpecialRegisters.Cr2 = AR::CpuFunctions::ReadControlRegister(2);
CpuState->SpecialRegisters.Cr3 = AR::CpuFunctions::ReadControlRegister(3);
CpuState->SpecialRegisters.Cr4 = AR::CpuFunctions::ReadControlRegister(4);
CpuState->SpecialRegisters.Cr8 = AR::CpuFunctions::ReadControlRegister(8);
/* Save DR registers */
CpuState->SpecialRegisters.KernelDr0 = AR::CpuFunc::ReadDebugRegister(0);
CpuState->SpecialRegisters.KernelDr1 = AR::CpuFunc::ReadDebugRegister(1);
CpuState->SpecialRegisters.KernelDr2 = AR::CpuFunc::ReadDebugRegister(2);
CpuState->SpecialRegisters.KernelDr3 = AR::CpuFunc::ReadDebugRegister(3);
CpuState->SpecialRegisters.KernelDr6 = AR::CpuFunc::ReadDebugRegister(6);
CpuState->SpecialRegisters.KernelDr7 = AR::CpuFunc::ReadDebugRegister(7);
CpuState->SpecialRegisters.KernelDr0 = AR::CpuFunctions::ReadDebugRegister(0);
CpuState->SpecialRegisters.KernelDr1 = AR::CpuFunctions::ReadDebugRegister(1);
CpuState->SpecialRegisters.KernelDr2 = AR::CpuFunctions::ReadDebugRegister(2);
CpuState->SpecialRegisters.KernelDr3 = AR::CpuFunctions::ReadDebugRegister(3);
CpuState->SpecialRegisters.KernelDr6 = AR::CpuFunctions::ReadDebugRegister(6);
CpuState->SpecialRegisters.KernelDr7 = AR::CpuFunctions::ReadDebugRegister(7);
/* Save MSR registers */
CpuState->SpecialRegisters.MsrGsBase = AR::CpuFunc::ReadModelSpecificRegister(X86_MSR_GSBASE);
CpuState->SpecialRegisters.MsrGsSwap = AR::CpuFunc::ReadModelSpecificRegister(X86_MSR_KERNEL_GSBASE);
CpuState->SpecialRegisters.MsrCStar = AR::CpuFunc::ReadModelSpecificRegister(X86_MSR_CSTAR);
CpuState->SpecialRegisters.MsrLStar = AR::CpuFunc::ReadModelSpecificRegister(X86_MSR_LSTAR);
CpuState->SpecialRegisters.MsrStar = AR::CpuFunc::ReadModelSpecificRegister(X86_MSR_STAR);
CpuState->SpecialRegisters.MsrSyscallMask = AR::CpuFunc::ReadModelSpecificRegister(X86_MSR_FMASK);
CpuState->SpecialRegisters.MsrGsBase = AR::CpuFunctions::ReadModelSpecificRegister(X86_MSR_GSBASE);
CpuState->SpecialRegisters.MsrGsSwap = AR::CpuFunctions::ReadModelSpecificRegister(X86_MSR_KERNEL_GSBASE);
CpuState->SpecialRegisters.MsrCStar = AR::CpuFunctions::ReadModelSpecificRegister(X86_MSR_CSTAR);
CpuState->SpecialRegisters.MsrLStar = AR::CpuFunctions::ReadModelSpecificRegister(X86_MSR_LSTAR);
CpuState->SpecialRegisters.MsrStar = AR::CpuFunctions::ReadModelSpecificRegister(X86_MSR_STAR);
CpuState->SpecialRegisters.MsrSyscallMask = AR::CpuFunctions::ReadModelSpecificRegister(X86_MSR_FMASK);
/* Save XMM control/status register */
CpuState->SpecialRegisters.MxCsr = AR::CpuFunc::ReadMxCsrRegister();
CpuState->SpecialRegisters.MxCsr = AR::CpuFunctions::ReadMxCsrRegister();
/* Save GDT, IDT, LDT and TaskRegister */
AR::CpuFunc::StoreGlobalDescriptorTable(&CpuState->SpecialRegisters.Gdtr.Limit);
AR::CpuFunc::StoreInterruptDescriptorTable(&CpuState->SpecialRegisters.Idtr.Limit);
AR::CpuFunc::StoreLocalDescriptorTable(&CpuState->SpecialRegisters.Ldtr);
AR::CpuFunc::StoreTaskRegister(&CpuState->SpecialRegisters.Tr);
AR::CpuFunctions::StoreGlobalDescriptorTable(&CpuState->SpecialRegisters.Gdtr.Limit);
AR::CpuFunctions::StoreInterruptDescriptorTable(&CpuState->SpecialRegisters.Idtr.Limit);
AR::CpuFunctions::StoreLocalDescriptorTable(&CpuState->SpecialRegisters.Ldtr);
AR::CpuFunctions::StoreTaskRegister(&CpuState->SpecialRegisters.Tr);
}

4
xtoskrnl/ke/crash.cc
View File

@@ -24,8 +24,8 @@ KE::Crash::HaltSystem(VOID)
for(;;)
{
/* Halt system */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunc::Halt();
AR::CpuFunctions::ClearInterruptFlag();
AR::CpuFunctions::Halt();
}
}

38
xtoskrnl/ke/i686/proc.cc
View File

@@ -21,7 +21,7 @@ PKPROCESSOR_BLOCK
KE::Processor::GetCurrentProcessorBlock(VOID)
{
/* Get processor block from FS register */
return (PKPROCESSOR_BLOCK)AR::CpuFunc::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Self));
return (PKPROCESSOR_BLOCK)AR::CpuFunctions::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Self));
}
/**
@@ -35,7 +35,7 @@ XTAPI
PKPROCESSOR_CONTROL_BLOCK
KE::Processor::GetCurrentProcessorControlBlock(VOID)
{
return (PKPROCESSOR_CONTROL_BLOCK)AR::CpuFunc::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CurrentPrcb));
return (PKPROCESSOR_CONTROL_BLOCK)AR::CpuFunctions::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CurrentPrcb));
}
/**
@@ -49,7 +49,7 @@ XTAPI
ULONG
KE::Processor::GetCurrentProcessorNumber(VOID)
{
return (ULONG)AR::CpuFunc::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CpuNumber));
return (ULONG)AR::CpuFunctions::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, CpuNumber));
}
/**
@@ -63,7 +63,7 @@ XTAPI
PKTHREAD
KE::Processor::GetCurrentThread(VOID)
{
return (PKTHREAD)AR::CpuFunc::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Prcb.CurrentThread));
return (PKTHREAD)AR::CpuFunctions::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, Prcb.CurrentThread));
}
/**
@@ -158,7 +158,7 @@ KE::Processor::RegisterHardwareId(IN ULONG HardwareId)
* Specifies the logical processor number.
*
* @param ProcessorBlock
* Supplies a pointer to the processor block.
* Supplies a pointer to the processor block.
*
* @return This routine does not return any value.
*
@@ -192,22 +192,22 @@ VOID
KE::Processor::SaveProcessorState(OUT PKPROCESSOR_STATE CpuState)
{
/* Save CR registers */
CpuState->SpecialRegisters.Cr0 = AR::CpuFunc::ReadControlRegister(0);
CpuState->SpecialRegisters.Cr2 = AR::CpuFunc::ReadControlRegister(2);
CpuState->SpecialRegisters.Cr3 = AR::CpuFunc::ReadControlRegister(3);
CpuState->SpecialRegisters.Cr4 = AR::CpuFunc::ReadControlRegister(4);
CpuState->SpecialRegisters.Cr0 = AR::CpuFunctions::ReadControlRegister(0);
CpuState->SpecialRegisters.Cr2 = AR::CpuFunctions::ReadControlRegister(2);
CpuState->SpecialRegisters.Cr3 = AR::CpuFunctions::ReadControlRegister(3);
CpuState->SpecialRegisters.Cr4 = AR::CpuFunctions::ReadControlRegister(4);
/* Save DR registers */
CpuState->SpecialRegisters.KernelDr0 = AR::CpuFunc::ReadDebugRegister(0);
CpuState->SpecialRegisters.KernelDr1 = AR::CpuFunc::ReadDebugRegister(1);
CpuState->SpecialRegisters.KernelDr2 = AR::CpuFunc::ReadDebugRegister(2);
CpuState->SpecialRegisters.KernelDr3 = AR::CpuFunc::ReadDebugRegister(3);
CpuState->SpecialRegisters.KernelDr6 = AR::CpuFunc::ReadDebugRegister(6);
CpuState->SpecialRegisters.KernelDr7 = AR::CpuFunc::ReadDebugRegister(7);
CpuState->SpecialRegisters.KernelDr0 = AR::CpuFunctions::ReadDebugRegister(0);
CpuState->SpecialRegisters.KernelDr1 = AR::CpuFunctions::ReadDebugRegister(1);
CpuState->SpecialRegisters.KernelDr2 = AR::CpuFunctions::ReadDebugRegister(2);
CpuState->SpecialRegisters.KernelDr3 = AR::CpuFunctions::ReadDebugRegister(3);
CpuState->SpecialRegisters.KernelDr6 = AR::CpuFunctions::ReadDebugRegister(6);
CpuState->SpecialRegisters.KernelDr7 = AR::CpuFunctions::ReadDebugRegister(7);
/* Save GDT, IDT, LDT and TaskRegister */
AR::CpuFunc::StoreGlobalDescriptorTable(&CpuState->SpecialRegisters.Gdtr.Limit);
AR::CpuFunc::StoreInterruptDescriptorTable(&CpuState->SpecialRegisters.Idtr.Limit);
AR::CpuFunc::StoreLocalDescriptorTable(&CpuState->SpecialRegisters.Ldtr);
AR::CpuFunc::StoreTaskRegister(&CpuState->SpecialRegisters.Tr);
AR::CpuFunctions::StoreGlobalDescriptorTable(&CpuState->SpecialRegisters.Gdtr.Limit);
AR::CpuFunctions::StoreInterruptDescriptorTable(&CpuState->SpecialRegisters.Idtr.Limit);
AR::CpuFunctions::StoreLocalDescriptorTable(&CpuState->SpecialRegisters.Ldtr);
AR::CpuFunctions::StoreTaskRegister(&CpuState->SpecialRegisters.Tr);
}

8
xtoskrnl/ke/spinlock.cc
View File

@@ -49,12 +49,12 @@ KE::SpinLock::AcquireSpinLock(IN OUT PKSPIN_LOCK SpinLock)
while(*(VOLATILE PKSPIN_LOCK)SpinLock & 1)
{
/* Yield processor and keep waiting */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}
/* Add an explicit memory barrier */
AR::CpuFunc::ReadWriteBarrier();
AR::CpuFunctions::ReadWriteBarrier();
}
/**
@@ -183,7 +183,7 @@ KE::SpinLock::ReleaseSpinLock(IN OUT PKSPIN_LOCK SpinLock)
RTL::Atomic::And32((PLONG)SpinLock, 0);
/* Add an explicit memory barrier */
AR::CpuFunc::ReadWriteBarrier();
AR::CpuFunctions::ReadWriteBarrier();
}
/**
@@ -204,7 +204,7 @@ TestSpinLock(IN PKSPIN_LOCK SpinLock)
if(*SpinLock)
{
/* Spinlock is busy, yield processor and return FALSE */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
return FALSE;
}

10
xtoskrnl/ke/sysres.cc
View File

@@ -62,10 +62,10 @@ KE::SystemResources::GetSystemResource(IN SYSTEM_RESOURCE_TYPE ResourceType,
Status = STATUS_SUCCESS;
/* Check if interrupts are enabled */
Interrupts = AR::CpuFunc::InterruptsEnabled();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
/* Disable interrupts and acquire a spinlock */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
KE::SpinLock::AcquireSpinLock(&ResourcesLock);
/* Iterate through system resources list */
@@ -114,7 +114,7 @@ KE::SystemResources::GetSystemResource(IN SYSTEM_RESOURCE_TYPE ResourceType,
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/* Return resource header and status code */
@@ -220,7 +220,7 @@ VOID
KE::SystemResources::ReleaseResource(IN PSYSTEM_RESOURCE_HEADER ResourceHeader)
{
/* Disable interrupts and acquire a spinlock */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
KE::SpinLock::AcquireSpinLock(&ResourcesLock);
/* Release resource lock */
@@ -228,5 +228,5 @@ KE::SystemResources::ReleaseResource(IN PSYSTEM_RESOURCE_HEADER ResourceHeader)
/* Release spinlock and enable interrupts */
KE::SpinLock::ReleaseSpinLock(&ResourcesLock);
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}

2
xtoskrnl/mm/amd64/paging.cc
View File

@@ -22,7 +22,7 @@ BOOLEAN
MM::Paging::GetExtendedPhysicalAddressingStatus(VOID)
{
/* Check if LA57 is enabled */
return ((AR::CpuFunc::ReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
return ((AR::CpuFunctions::ReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
}
/**

4
xtoskrnl/mm/amd64/pte.cc
View File

@@ -99,7 +99,7 @@ MM::Pte::InitializePageTable(VOID)
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Enable the Global Paging (PGE) feature */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PGE);
AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_PGE);
/* Check XPA status */
if(Xpa)
@@ -123,7 +123,7 @@ MM::Pte::InitializePageTable(VOID)
}
/* Flush the TLB to invalidate all non-global entries */
AR::CpuFunc::FlushTlb();
AR::CpuFunctions::FlushTlb();
/* Create a template PTE for mapping kernel pages */
MM::Paging::ClearPte(&TemplatePte);

2
xtoskrnl/mm/i686/paging.cc
View File

@@ -22,7 +22,7 @@ BOOLEAN
MM::Paging::GetExtendedPhysicalAddressingStatus(VOID)
{
/* Check if PAE is enabled */
return ((AR::CpuFunc::ReadControlRegister(4) & CR4_PAE) != 0) ? TRUE : FALSE;
return ((AR::CpuFunctions::ReadControlRegister(4) & CR4_PAE) != 0) ? TRUE : FALSE;
}
/**

4
xtoskrnl/mm/i686/pfn.cc
View File

@@ -150,7 +150,7 @@ MM::Pfn::InitializePageTablePfns(VOID)
RootLevel = 3;
/* Retrieve the PFN of the PML3 table and its virtual base address */
PageFrameIndex = AR::CpuFunc::ReadControlRegister(3) >> MM_PAGE_SHIFT;
PageFrameIndex = AR::CpuFunctions::ReadControlRegister(3) >> MM_PAGE_SHIFT;
RootPte = (PMMPTE)MM::Paging::GetPpeAddress(NULLPTR);
}
else
@@ -159,7 +159,7 @@ MM::Pfn::InitializePageTablePfns(VOID)
RootLevel = 2;
/* Retrieve the PFN of the PML2 table and its virtual base address */
PageFrameIndex = AR::CpuFunc::ReadControlRegister(3) >> MM_PAGE_SHIFT;
PageFrameIndex = AR::CpuFunctions::ReadControlRegister(3) >> MM_PAGE_SHIFT;
RootPte = (PMMPTE)MM::Paging::GetPdeAddress(NULLPTR);
}

6
xtoskrnl/mm/i686/pte.cc
View File

@@ -70,13 +70,13 @@ MM::Pte::InitializePageTable(VOID)
/* Get CPU features */
CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Check if Paging Global Extensions (PGE) is supported */
if(CpuRegisters.Edx & CPUID_FEATURES_EDX_PGE)
{
/* Enable the Global Paging (PGE) feature */
AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PGE);
AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_PGE);
}
/* Get the PD user-space range for both legacy and PAE paging */
@@ -91,7 +91,7 @@ MM::Pte::InitializePageTable(VOID)
}
/* Flush the TLB to invalidate all non-global entries */
AR::CpuFunc::FlushTlb();
AR::CpuFunctions::FlushTlb();
/* Create a template PTE for mapping kernel pages */
MM::Paging::ClearPte(&TemplatePte);

2
xtoskrnl/mm/mmgr.cc
View File

@@ -279,7 +279,7 @@ MM::Manager::InitializeMemoryManager(VOID)
MM::Pool::InitializePagedPool();
/* Flush TLB */
AR::CpuFunc::FlushTlb();
AR::CpuFunctions::FlushTlb();
}
/**

18
xtoskrnl/mm/paging.cc
View File

@@ -98,39 +98,39 @@ MM::Paging::FlushTlb(VOID)
ULONG_PTR Cr4;
/* Save interrupts state and disable them */
Interrupts = AR::CpuFunc::InterruptsEnabled();
AR::CpuFunc::ClearInterruptFlag();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
AR::CpuFunctions::ClearInterruptFlag();
/* Get CPU features */
CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Check if Paging Global Extensions (PGE) is supported */
if(CpuRegisters.Edx & CPUID_FEATURES_EDX_PGE)
{
/* Read CR4 */
Cr4 = AR::CpuFunc::ReadControlRegister(4);
Cr4 = AR::CpuFunctions::ReadControlRegister(4);
/* Disable PGE */
AR::CpuFunc::WriteControlRegister(4, Cr4 & ~CR4_PGE);
AR::CpuFunctions::WriteControlRegister(4, Cr4 & ~CR4_PGE);
/* Flush the TLB */
AR::CpuFunc::FlushTlb();
AR::CpuFunctions::FlushTlb();
/* Restore CR4 */
AR::CpuFunc::WriteControlRegister(4, Cr4);
AR::CpuFunctions::WriteControlRegister(4, Cr4);
}
else
{
/* Simply flush the TLB */
AR::CpuFunc::FlushTlb();
AR::CpuFunctions::FlushTlb();
}
/* Check if interrupts should be enabled */
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
}

2
xtoskrnl/mm/pte.cc
View File

@@ -539,7 +539,7 @@ MM::Pte::ReserveSystemPtes(IN PFN_COUNT NumberOfPtes,
TotalSystemFreePtes[SystemPtePoolType] -= NumberOfPtes;
/* Flush the TLB to ensure address translation consistency */
AR::CpuFunc::FlushTlb();
AR::CpuFunctions::FlushTlb();
/* Return a pointer to the start of the reserved PTE block */
return ReservedPte;

4
xtoskrnl/rtl/amd64/exsup.cc
View File

@@ -73,7 +73,7 @@ __CxxFrameHandler3(IN PEXCEPTION_RECORD ExceptionRecord,
UNIMPLEMENTED;
/* Disable interrupts and hang */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
KE::Crash::Panic(0);
/* Continue search */
@@ -128,6 +128,6 @@ _purecall(VOID)
UNIMPLEMENTED;
/* Disable interrupts and hang */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
KE::Crash::Panic(0);
}

4
xtoskrnl/rtl/i686/exsup.cc
View File

@@ -73,7 +73,7 @@ __CxxFrameHandler3(IN PEXCEPTION_RECORD ExceptionRecord,
UNIMPLEMENTED;
/* Disable interrupts and hang */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
KE::Crash::Panic(0);
/* Continue search */
@@ -128,6 +128,6 @@ _purecall(VOID)
UNIMPLEMENTED;
/* Disable interrupts and hang */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
KE::Crash::Panic(0);
}