Rename architecture CPU functions class

xtoskrnl/ar/amd64/cpufunc.cc

@@ -18,7 +18,7 @@
  */
 XTCDECL
 VOID
-AR::CpuFunc::ClearInterruptFlag(VOID)
+AR::CpuFunctions::ClearInterruptFlag(VOID)
 {
     __asm__ volatile("cli");
 }
@@ -35,7 +35,7 @@ AR::CpuFunc::ClearInterruptFlag(VOID)
  */
 XTCDECL
 BOOLEAN
-AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
+AR::CpuFunctions::CpuId(IN OUT PCPUID_REGISTERS Registers)
 {
     UINT32 MaxLeaf;
 
@@ -76,7 +76,7 @@ AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
  */
 XTCDECL
 VOID
-AR::CpuFunc::FlushTlb(VOID)
+AR::CpuFunctions::FlushTlb(VOID)
 {
     /* Flush the TLB by resetting the CR3 */
     WriteControlRegister(3, ReadControlRegister(3));
@@ -91,7 +91,7 @@ AR::CpuFunc::FlushTlb(VOID)
  */
 XTCDECL
 ULONG
-AR::CpuFunc::GetCpuFlags(VOID)
+AR::CpuFunctions::GetCpuFlags(VOID)
 {
     ULONG_PTR Flags;
 
@@ -116,7 +116,7 @@ AR::CpuFunc::GetCpuFlags(VOID)
 XTASSEMBLY
 XTCDECL
 ULONG_PTR
-AR::CpuFunc::GetStackPointer(VOID)
+AR::CpuFunctions::GetStackPointer(VOID)
 {
     /* Get current stack pointer */
     __asm__ volatile("movq %%rsp, %%rax\n"
@@ -135,7 +135,7 @@ AR::CpuFunc::GetStackPointer(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::Halt(VOID)
+AR::CpuFunctions::Halt(VOID)
 {
     __asm__ volatile("hlt");
 }
@@ -149,7 +149,7 @@ AR::CpuFunc::Halt(VOID)
  */
 XTCDECL
 BOOLEAN
-AR::CpuFunc::InterruptsEnabled(VOID)
+AR::CpuFunctions::InterruptsEnabled(VOID)
 {
     ULONG_PTR Flags;
 
@@ -172,7 +172,7 @@ AR::CpuFunc::InterruptsEnabled(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::InvalidateTlbEntry(IN PVOID Address)
+AR::CpuFunctions::InvalidateTlbEntry(IN PVOID Address)
 {
     __asm__ volatile("invlpg (%0)"
                      :
@@ -192,7 +192,7 @@ AR::CpuFunc::InvalidateTlbEntry(IN PVOID Address)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
+AR::CpuFunctions::LoadGlobalDescriptorTable(IN PVOID Source)
 {
     __asm__ volatile("lgdt %0"
                      :
@@ -212,7 +212,7 @@ AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
+AR::CpuFunctions::LoadInterruptDescriptorTable(IN PVOID Source)
 {
     __asm__ volatile("lidt %0"
                      :
@@ -232,7 +232,7 @@ AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
+AR::CpuFunctions::LoadLocalDescriptorTable(IN USHORT Source)
 {
     __asm__ volatile("lldtw %0"
                      :
@@ -251,7 +251,7 @@ AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadMxcsrRegister(IN ULONG Source)
+AR::CpuFunctions::LoadMxcsrRegister(IN ULONG Source)
 {
     __asm__ volatile("ldmxcsr %0"
                      :
@@ -273,7 +273,7 @@ AR::CpuFunc::LoadMxcsrRegister(IN ULONG Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadSegment(IN USHORT Segment,
+AR::CpuFunctions::LoadSegment(IN USHORT Segment,
                      IN ULONG Source)
 {
     switch(Segment)
@@ -335,7 +335,7 @@ AR::CpuFunc::LoadSegment(IN USHORT Segment,
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadTaskRegister(USHORT Source)
+AR::CpuFunctions::LoadTaskRegister(USHORT Source)
 {
     __asm__ volatile("ltr %0"
                      :
@@ -351,7 +351,7 @@ AR::CpuFunc::LoadTaskRegister(USHORT Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::MemoryBarrier(VOID)
+AR::CpuFunctions::MemoryBarrier(VOID)
 {
     LONG Barrier;
     __asm__ volatile("lock; orl $0, %0;"
@@ -371,7 +371,7 @@ AR::CpuFunc::MemoryBarrier(VOID)
  */
 XTCDECL
 ULONG_PTR
-AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
+AR::CpuFunctions::ReadControlRegister(IN USHORT ControlRegister)
 {
     ULONG_PTR Value;
 
@@ -435,7 +435,7 @@ AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
  */
 XTCDECL
 ULONG_PTR
-AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
+AR::CpuFunctions::ReadDebugRegister(IN USHORT DebugRegister)
 {
     ULONG_PTR Value;
 
@@ -504,7 +504,7 @@ AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
  */
 XTCDECL
 ULONGLONG
-AR::CpuFunc::ReadGSQuadWord(ULONG Offset)
+AR::CpuFunctions::ReadGSQuadWord(ULONG Offset)
 {
     ULONGLONG Value;
 
@@ -527,7 +527,7 @@ AR::CpuFunc::ReadGSQuadWord(ULONG Offset)
  */
 XTCDECL
 ULONGLONG
-AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
+AR::CpuFunctions::ReadModelSpecificRegister(IN ULONG Register)
 {
     ULONG Low, High;
 
@@ -548,7 +548,7 @@ AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
  */
 XTCDECL
 UINT
-AR::CpuFunc::ReadMxCsrRegister(VOID)
+AR::CpuFunctions::ReadMxCsrRegister(VOID)
 {
     return __builtin_ia32_stmxcsr();
 }
@@ -562,7 +562,7 @@ AR::CpuFunc::ReadMxCsrRegister(VOID)
  */
 XTCDECL
 ULONGLONG
-AR::CpuFunc::ReadTimeStampCounter(VOID)
+AR::CpuFunctions::ReadTimeStampCounter(VOID)
 {
     ULONGLONG Low, High;
 
@@ -585,7 +585,7 @@ AR::CpuFunc::ReadTimeStampCounter(VOID)
  */
 XTCDECL
 ULONGLONG
-AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
+AR::CpuFunctions::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
 {
     ULONG Low, High;
 
@@ -609,7 +609,7 @@ AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
  */
 XTCDECL
 VOID
-AR::CpuFunc::ReadWriteBarrier(VOID)
+AR::CpuFunctions::ReadWriteBarrier(VOID)
 {
     __asm__ volatile(""
                      :
@@ -626,7 +626,7 @@ AR::CpuFunc::ReadWriteBarrier(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::SetInterruptFlag(VOID)
+AR::CpuFunctions::SetInterruptFlag(VOID)
 {
     __asm__ volatile("sti");
 }
@@ -643,7 +643,7 @@ AR::CpuFunc::SetInterruptFlag(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
+AR::CpuFunctions::StoreGlobalDescriptorTable(OUT PVOID Destination)
 {
     __asm__ volatile("sgdt %0"
                      : "=m" (*(PSHORT)Destination)
@@ -663,7 +663,7 @@ AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
+AR::CpuFunctions::StoreInterruptDescriptorTable(OUT PVOID Destination)
 {
     __asm__ volatile("sidt %0"
                      : "=m" (*(PSHORT)Destination)
@@ -683,7 +683,7 @@ AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
+AR::CpuFunctions::StoreLocalDescriptorTable(OUT PVOID Destination)
 {
     __asm__ volatile("sldt %0"
                      : "=m" (*(PSHORT)Destination)
@@ -706,8 +706,8 @@ AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreSegment(IN USHORT Segment,
-                          OUT PVOID Destination)
+AR::CpuFunctions::StoreSegment(IN USHORT Segment,
+                               OUT PVOID Destination)
 {
     switch(Segment)
     {
@@ -753,7 +753,7 @@ AR::CpuFunc::StoreSegment(IN USHORT Segment,
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
+AR::CpuFunctions::StoreTaskRegister(OUT PVOID Destination)
 {
     __asm__ volatile("str %0"
                      : "=m" (*(PULONG)Destination)
@@ -776,8 +776,8 @@ AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
-                              IN UINT_PTR Value)
+AR::CpuFunctions::WriteControlRegister(IN USHORT ControlRegister,
+                                       IN UINT_PTR Value)
 {
     /* Write a value into specified control register */
     switch(ControlRegister)
@@ -835,8 +835,8 @@ AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
-                            IN UINT_PTR Value)
+AR::CpuFunctions::WriteDebugRegister(IN USHORT DebugRegister,
+                                     IN UINT_PTR Value)
 {
     /* Write a value into specified debug register */
     switch(DebugRegister)
@@ -912,7 +912,7 @@ AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
+AR::CpuFunctions::WriteEflagsRegister(IN UINT_PTR Value)
 {
     __asm__ volatile("push %0\n"
                      "popf"
@@ -935,8 +935,8 @@ AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
-                                    IN ULONGLONG Value)
+AR::CpuFunctions::WriteModelSpecificRegister(IN ULONG Register,
+                                             IN ULONGLONG Value)
 {
     ULONG Low = Value & 0xFFFFFFFF;
     ULONG High = Value >> 32;
@@ -957,7 +957,7 @@ AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
  */
 XTCDECL
 VOID
-AR::CpuFunc::YieldProcessor(VOID)
+AR::CpuFunctions::YieldProcessor(VOID)
 {
     __asm__ volatile("pause"
                      :

xtoskrnl/ar/amd64/procsup.cc

@@ -75,7 +75,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
     /* Get CPU vendor by issueing CPUID instruction */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
 
     /* Store CPU vendor in processor control block */
     Prcb->CpuId.Vendor = (CPU_VENDOR)CpuRegisters.Ebx;
@@ -87,7 +87,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
     /* Get CPU standard features */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
 
     /* Store CPU signature in processor control block */
     CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
@@ -149,13 +149,13 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
     /* Get maximum CPUID standard leaf */
     RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
     MaxStandardLeaf = CpuRegisters.Eax;
 
     /* Get maximum CPUID extended leaf */
     RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_EXTENDED_MAX;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
     MaxExtendedLeaf = CpuRegisters.Eax;
 
     /* Check if CPU supports standard features leaf */
@@ -164,7 +164,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU standard features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU standard features in processor control block */
         if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SSE3) Prcb->CpuId.FeatureBits |= KCF_SSE3;
@@ -208,7 +208,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU standard features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_STANDARD7_FEATURES;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU standard7 features in processor control block */
         if(CpuRegisters.Ebx & CPUID_FEATURES_EBX_FSGSBASE) Prcb->CpuId.FeatureBits |= KCF_FSGSBASE;
@@ -226,7 +226,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU power management features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_POWER_MANAGEMENT;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU power management features in processor control block */
         if(CpuRegisters.Eax & CPUID_FEATURES_EAX_ARAT) Prcb->CpuId.FeatureBits |= KCF_ARAT;
@@ -238,7 +238,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU extended features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_EXTENDED_FEATURES;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU extended features in processor control block */
         if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SVM) Prcb->CpuId.ExtendedFeatureBits |= KCF_SVM;
@@ -259,7 +259,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU advanced power management features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_ADVANCED_POWER_MANAGEMENT;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU advanced power management features in processor control block */
         if(CpuRegisters.Edx & CPUID_FEATURES_EDX_TSCI) Prcb->CpuId.ExtendedFeatureBits |= KCF_INVARIANT_TSC;
@@ -401,16 +401,16 @@ AR::ProcessorSupport::InitializeProcessor(IN PVOID ProcessorStructures)
     IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
 
     /* Load GDT, IDT and TSS */
-    AR::CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
-    AR::CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
-    AR::CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
+    AR::CpuFunctions::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
+    AR::CpuFunctions::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
+    AR::CpuFunctions::LoadTaskRegister((UINT)KGDT_SYS_TSS);
 
     /* Initialize segment registers */
     InitializeSegments();
 
     /* Set GS base */
-    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
-    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
+    AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_GSBASE, (ULONGLONG)ProcessorBlock);
+    AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_KERNEL_GSBASE, (ULONGLONG)ProcessorBlock);
 
     /* Initialize processor registers */
     InitializeProcessorRegisters();
@@ -495,45 +495,46 @@ AR::ProcessorSupport::InitializeProcessorRegisters(VOID)
     ULONGLONG PatAttributes;
 
     /* Enable FXSAVE restore */
-    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_FXSR);
+    AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_FXSR);
 
     /* Enable XMMI exceptions */
-    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_XMMEXCPT);
+    AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_XMMEXCPT);
 
     /* Set debugger extension */
-    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_DE);
+    AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_DE);
 
     /* Enable large pages */
-    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PSE);
+    AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_PSE);
 
     /* Enable write-protection */
-    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_WP);
+    AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) | CR0_WP);
 
     /* Set alignment mask */
-    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_AM);
+    AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) | CR0_AM);
 
     /* Disable FPU monitoring */
-    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) & ~CR0_MP);
+    AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) & ~CR0_MP);
 
     /* Disable x87 FPU exceptions */
-    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) & ~CR0_NE);
+    AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) & ~CR0_NE);
 
     /* Flush the TLB */
-    AR::CpuFunc::FlushTlb();
+    AR::CpuFunctions::FlushTlb();
 
     /* Initialize system call MSRs */
     AR::Traps::InitializeSystemCallMsrs();
     
     /* Enable No-Execute (NXE) in EFER MSR */
-    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunc::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
+    AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_EFER,
+                                                 CpuFunctions::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_NXE);
 
     /* Initialize Page Attribute Table */
     PatAttributes = (PAT_TYPE_WB << 0) | (PAT_TYPE_USWC << 8) | (PAT_TYPE_WEAK_UC << 16) | (PAT_TYPE_STRONG_UC << 24) |
                     (PAT_TYPE_WB << 32) | (PAT_TYPE_USWC << 40) | (PAT_TYPE_WEAK_UC << 48) | (PAT_TYPE_STRONG_UC << 56);
-    AR::CpuFunc::WriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
+    AR::CpuFunctions::WriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
 
     /* Initialize MXCSR register */
-    AR::CpuFunc::LoadMxcsrRegister(INITIAL_MXCSR);
+    AR::CpuFunctions::LoadMxcsrRegister(INITIAL_MXCSR);
 }
 
 /**
@@ -634,12 +635,12 @@ VOID
 AR::ProcessorSupport::InitializeSegments(VOID)
 {
     /* Initialize segments */
-    AR::CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
-    AR::CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
-    AR::CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
-    AR::CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R3_CMTEB | RPL_MASK);
-    AR::CpuFunc::LoadSegment(SEGMENT_GS, KGDT_R3_DATA | RPL_MASK);
-    AR::CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
+    AR::CpuFunctions::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
+    AR::CpuFunctions::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunctions::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunctions::LoadSegment(SEGMENT_FS, KGDT_R3_CMTEB | RPL_MASK);
+    AR::CpuFunctions::LoadSegment(SEGMENT_GS, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunctions::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
 }
 
 /**

xtoskrnl/ar/amd64/traps.cc

@@ -26,8 +26,8 @@ AR::Traps::DispatchInterrupt(IN PKTRAP_FRAME TrapFrame)
     PINTERRUPT_HANDLER Handler;
 
     /* Read the handler pointer from the CPU's interrupt dispatch table */
-    Handler = (PINTERRUPT_HANDLER)AR::CpuFunc::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
-                                                              (TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
+    Handler = (PINTERRUPT_HANDLER)AR::CpuFunctions::ReadGSQuadWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
+                                                                   (TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
 
     /* Check if the interrupt has a handler registered */
     if(Handler != NULLPTR)
@@ -672,13 +672,13 @@ VOID
 AR::Traps::InitializeSystemCallMsrs(VOID)
 {
     /* Initialize system calls MSR */
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_STAR, (((ULONG64)KGDT_R3_CMCODE | RPL_MASK) << 48) | ((ULONG64)KGDT_R0_CODE << 32));
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_CSTAR, (ULONG64)&HandleSystemCall32);
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_LSTAR, (ULONG64)&HandleSystemCall64);
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_FMASK, X86_EFLAGS_IF_MASK | X86_EFLAGS_TF_MASK);
+    CpuFunctions::WriteModelSpecificRegister(X86_MSR_STAR, (((ULONG64)KGDT_R3_CMCODE | RPL_MASK) << 48) | ((ULONG64)KGDT_R0_CODE << 32));
+    CpuFunctions::WriteModelSpecificRegister(X86_MSR_CSTAR, (ULONG64)&HandleSystemCall32);
+    CpuFunctions::WriteModelSpecificRegister(X86_MSR_LSTAR, (ULONG64)&HandleSystemCall64);
+    CpuFunctions::WriteModelSpecificRegister(X86_MSR_FMASK, X86_EFLAGS_IF_MASK | X86_EFLAGS_TF_MASK);
 
     /* Enable system call extensions (SCE) in EFER MSR */
-    CpuFunc::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunc::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
+    CpuFunctions::WriteModelSpecificRegister(X86_MSR_EFER, CpuFunctions::ReadModelSpecificRegister(X86_MSR_EFER) | X86_MSR_EFER_SCE);
 }
 
 /**