Rename architecture CPU functions class

xtoskrnl/ar/i686/cpufunc.cc

@@ -18,7 +18,7 @@
  */
 XTCDECL
 VOID
-AR::CpuFunc::ClearInterruptFlag(VOID)
+AR::CpuFunctions::ClearInterruptFlag(VOID)
 {
     __asm__ volatile("cli");
 }
@@ -35,7 +35,7 @@ AR::CpuFunc::ClearInterruptFlag(VOID)
  */
 XTCDECL
 BOOLEAN
-AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
+AR::CpuFunctions::CpuId(IN OUT PCPUID_REGISTERS Registers)
 {
     UINT32 MaxLeaf;
 
@@ -76,7 +76,7 @@ AR::CpuFunc::CpuId(IN OUT PCPUID_REGISTERS Registers)
  */
 XTCDECL
 VOID
-AR::CpuFunc::FlushTlb(VOID)
+AR::CpuFunctions::FlushTlb(VOID)
 {
     /* Flush the TLB by resetting the CR3 */
     WriteControlRegister(3, ReadControlRegister(3));
@@ -91,7 +91,7 @@ AR::CpuFunc::FlushTlb(VOID)
  */
 XTCDECL
 ULONG
-AR::CpuFunc::GetCpuFlags(VOID)
+AR::CpuFunctions::GetCpuFlags(VOID)
 {
     ULONG_PTR Flags;
 
@@ -116,7 +116,7 @@ AR::CpuFunc::GetCpuFlags(VOID)
 XTASSEMBLY
 XTCDECL
 ULONG_PTR
-AR::CpuFunc::GetStackPointer(VOID)
+AR::CpuFunctions::GetStackPointer(VOID)
 {
     /* Get current stack pointer */
     __asm__ volatile("mov %%esp, %%eax\n"
@@ -135,7 +135,7 @@ AR::CpuFunc::GetStackPointer(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::Halt(VOID)
+AR::CpuFunctions::Halt(VOID)
 {
     __asm__ volatile("hlt");
 }
@@ -149,7 +149,7 @@ AR::CpuFunc::Halt(VOID)
  */
 XTCDECL
 BOOLEAN
-AR::CpuFunc::InterruptsEnabled(VOID)
+AR::CpuFunctions::InterruptsEnabled(VOID)
 {
     ULONG_PTR Flags;
 
@@ -172,7 +172,7 @@ AR::CpuFunc::InterruptsEnabled(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::InvalidateTlbEntry(PVOID Address)
+AR::CpuFunctions::InvalidateTlbEntry(PVOID Address)
 {
     __asm__ volatile("invlpg (%0)"
                      :
@@ -192,7 +192,7 @@ AR::CpuFunc::InvalidateTlbEntry(PVOID Address)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
+AR::CpuFunctions::LoadGlobalDescriptorTable(IN PVOID Source)
 {
     __asm__ volatile("lgdt %0"
                      :
@@ -212,7 +212,7 @@ AR::CpuFunc::LoadGlobalDescriptorTable(IN PVOID Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
+AR::CpuFunctions::LoadInterruptDescriptorTable(IN PVOID Source)
 {
     __asm__ volatile("lidt %0"
                      :
@@ -232,7 +232,7 @@ AR::CpuFunc::LoadInterruptDescriptorTable(IN PVOID Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
+AR::CpuFunctions::LoadLocalDescriptorTable(IN USHORT Source)
 {
     __asm__ volatile("lldtw %0"
                      :
@@ -254,8 +254,8 @@ AR::CpuFunc::LoadLocalDescriptorTable(IN USHORT Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadSegment(IN USHORT Segment,
-                         IN ULONG Source)
+AR::CpuFunctions::LoadSegment(IN USHORT Segment,
+                              IN ULONG Source)
 {
     switch(Segment)
     {
@@ -316,7 +316,7 @@ AR::CpuFunc::LoadSegment(IN USHORT Segment,
  */
 XTCDECL
 VOID
-AR::CpuFunc::LoadTaskRegister(USHORT Source)
+AR::CpuFunctions::LoadTaskRegister(USHORT Source)
 {
     __asm__ volatile("ltr %0"
                      :
@@ -332,7 +332,7 @@ AR::CpuFunc::LoadTaskRegister(USHORT Source)
  */
 XTCDECL
 VOID
-AR::CpuFunc::MemoryBarrier(VOID)
+AR::CpuFunctions::MemoryBarrier(VOID)
 {
    LONG Barrier;
    __asm__ volatile("xchg %%eax, %0"
@@ -353,7 +353,7 @@ AR::CpuFunc::MemoryBarrier(VOID)
  */
 XTCDECL
 ULONG_PTR
-AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
+AR::CpuFunctions::ReadControlRegister(IN USHORT ControlRegister)
 {
     ULONG_PTR Value;
 
@@ -410,7 +410,7 @@ AR::CpuFunc::ReadControlRegister(IN USHORT ControlRegister)
  */
 XTCDECL
 ULONG_PTR
-AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
+AR::CpuFunctions::ReadDebugRegister(IN USHORT DebugRegister)
 {
     ULONG_PTR Value;
 
@@ -479,7 +479,7 @@ AR::CpuFunc::ReadDebugRegister(IN USHORT DebugRegister)
  */
 XTCDECL
 ULONG
-AR::CpuFunc::ReadFSDualWord(ULONG Offset)
+AR::CpuFunctions::ReadFSDualWord(ULONG Offset)
 {
     ULONG Value;
     __asm__ volatile("movl %%fs:%a[Offset], %k[Value]"
@@ -500,7 +500,7 @@ AR::CpuFunc::ReadFSDualWord(ULONG Offset)
  */
 XTCDECL
 ULONGLONG
-AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
+AR::CpuFunctions::ReadModelSpecificRegister(IN ULONG Register)
 {
     ULONGLONG Value;
 
@@ -519,7 +519,7 @@ AR::CpuFunc::ReadModelSpecificRegister(IN ULONG Register)
  */
 XTCDECL
 UINT
-AR::CpuFunc::ReadMxCsrRegister(VOID)
+AR::CpuFunctions::ReadMxCsrRegister(VOID)
 {
     return __builtin_ia32_stmxcsr();
 }
@@ -533,7 +533,7 @@ AR::CpuFunc::ReadMxCsrRegister(VOID)
  */
 XTCDECL
 ULONGLONG
-AR::CpuFunc::ReadTimeStampCounter(VOID)
+AR::CpuFunctions::ReadTimeStampCounter(VOID)
 {
     ULONGLONG Value;
 
@@ -555,7 +555,7 @@ AR::CpuFunc::ReadTimeStampCounter(VOID)
  */
 XTCDECL
 ULONGLONG
-AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
+AR::CpuFunctions::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
 {
     ULONG Low, High;
 
@@ -579,7 +579,7 @@ AR::CpuFunc::ReadTimeStampCounterProcessor(OUT PULONG TscAux)
  */
 XTCDECL
 VOID
-AR::CpuFunc::ReadWriteBarrier(VOID)
+AR::CpuFunctions::ReadWriteBarrier(VOID)
 {
     __asm__ volatile(""
                      :
@@ -596,7 +596,7 @@ AR::CpuFunc::ReadWriteBarrier(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::SetInterruptFlag(VOID)
+AR::CpuFunctions::SetInterruptFlag(VOID)
 {
     __asm__ volatile("sti");
 }
@@ -613,7 +613,7 @@ AR::CpuFunc::SetInterruptFlag(VOID)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
+AR::CpuFunctions::StoreGlobalDescriptorTable(OUT PVOID Destination)
 {
     __asm__ volatile("sgdt %0"
                      : "=m" (*(PSHORT)Destination)
@@ -633,7 +633,7 @@ AR::CpuFunc::StoreGlobalDescriptorTable(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
+AR::CpuFunctions::StoreInterruptDescriptorTable(OUT PVOID Destination)
 {
     __asm__ volatile("sidt %0"
                      : "=m" (*(PSHORT)Destination)
@@ -653,7 +653,7 @@ AR::CpuFunc::StoreInterruptDescriptorTable(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
+AR::CpuFunctions::StoreLocalDescriptorTable(OUT PVOID Destination)
 {
     __asm__ volatile("sldt %0"
                      : "=m" (*(PSHORT)Destination)
@@ -676,8 +676,8 @@ AR::CpuFunc::StoreLocalDescriptorTable(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreSegment(IN USHORT Segment,
-                          OUT PVOID Destination)
+AR::CpuFunctions::StoreSegment(IN USHORT Segment,
+                               OUT PVOID Destination)
 {
     switch(Segment)
     {
@@ -723,7 +723,7 @@ AR::CpuFunc::StoreSegment(IN USHORT Segment,
  */
 XTCDECL
 VOID
-AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
+AR::CpuFunctions::StoreTaskRegister(OUT PVOID Destination)
 {
     __asm__ volatile("str %0"
                      : "=m" (*(PULONG)Destination)
@@ -746,8 +746,8 @@ AR::CpuFunc::StoreTaskRegister(OUT PVOID Destination)
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
-                              IN UINT_PTR Value)
+AR::CpuFunctions::WriteControlRegister(IN USHORT ControlRegister,
+                                       IN UINT_PTR Value)
 {
     /* Write a value into specified control register */
     switch(ControlRegister)
@@ -798,8 +798,8 @@ AR::CpuFunc::WriteControlRegister(IN USHORT ControlRegister,
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
-                            IN UINT_PTR Value)
+AR::CpuFunctions::WriteDebugRegister(IN USHORT DebugRegister,
+                                     IN UINT_PTR Value)
 {
     /* Write a value into specified debug register */
     switch(DebugRegister)
@@ -867,7 +867,7 @@ AR::CpuFunc::WriteDebugRegister(IN USHORT DebugRegister,
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
+AR::CpuFunctions::WriteEflagsRegister(IN UINT_PTR Value)
 {
     __asm__ volatile("push %0\n"
                      "popf"
@@ -890,8 +890,8 @@ AR::CpuFunc::WriteEflagsRegister(IN UINT_PTR Value)
  */
 XTCDECL
 VOID
-AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
-                                    IN ULONGLONG Value)
+AR::CpuFunctions::WriteModelSpecificRegister(IN ULONG Register,
+                                             IN ULONGLONG Value)
 {
     __asm__ volatile("wrmsr"
                      :
@@ -908,7 +908,7 @@ AR::CpuFunc::WriteModelSpecificRegister(IN ULONG Register,
  */
 XTCDECL
 VOID
-AR::CpuFunc::YieldProcessor(VOID)
+AR::CpuFunctions::YieldProcessor(VOID)
 {
     __asm__ volatile("pause"
                      :

xtoskrnl/ar/i686/procsup.cc

@@ -68,7 +68,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
     /* Get CPU vendor by issueing CPUID instruction */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
 
     /* Store CPU vendor in processor control block */
     Prcb->CpuId.Vendor = (CPU_VENDOR)CpuRegisters.Ebx;
@@ -80,7 +80,7 @@ AR::ProcessorSupport::IdentifyProcessor(VOID)
     /* Get CPU standard features */
     RtlZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
 
     /* Store CPU signature in processor control block */
     CpuSignature = *(PCPUID_SIGNATURE)&CpuRegisters.Eax;
@@ -142,13 +142,13 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
     /* Get maximum CPUID standard leaf */
     RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
     MaxStandardLeaf = CpuRegisters.Eax;
 
     /* Get maximum CPUID extended leaf */
     RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
     CpuRegisters.Leaf = CPUID_GET_EXTENDED_MAX;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
     MaxExtendedLeaf = CpuRegisters.Eax;
 
     /* Check if CPU supports standard features leaf */
@@ -157,7 +157,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU standard features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU standard features in processor control block */
         if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SSE3) Prcb->CpuId.FeatureBits |= KCF_SSE3;
@@ -201,7 +201,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU standard features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_STANDARD7_FEATURES;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU standard7 features in processor control block */
         if(CpuRegisters.Ebx & CPUID_FEATURES_EBX_FSGSBASE) Prcb->CpuId.FeatureBits |= KCF_FSGSBASE;
@@ -219,7 +219,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU power management features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_POWER_MANAGEMENT;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU power management features in processor control block */
         if(CpuRegisters.Eax & CPUID_FEATURES_EAX_ARAT) Prcb->CpuId.FeatureBits |= KCF_ARAT;
@@ -231,7 +231,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU extended features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_EXTENDED_FEATURES;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU extended features in processor control block */
         if(CpuRegisters.Ecx & CPUID_FEATURES_ECX_SVM) Prcb->CpuId.ExtendedFeatureBits |= KCF_SVM;
@@ -252,7 +252,7 @@ AR::ProcessorSupport::IdentifyProcessorFeatures(VOID)
         /* Get CPU advanced power management features */
         RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
         CpuRegisters.Leaf = CPUID_GET_ADVANCED_POWER_MANAGEMENT;
-        AR::CpuFunc::CpuId(&CpuRegisters);
+        AR::CpuFunctions::CpuId(&CpuRegisters);
 
         /* Store CPU advanced power management features in processor control block */
         if(CpuRegisters.Edx & CPUID_FEATURES_EDX_TSCI) Prcb->CpuId.ExtendedFeatureBits |= KCF_INVARIANT_TSC;
@@ -397,9 +397,9 @@ AR::ProcessorSupport::InitializeProcessor(IN PVOID ProcessorStructures)
     IdtDescriptor.Limit = (IDT_ENTRIES * sizeof(KIDTENTRY)) - 1;
 
     /* Load GDT, IDT and TSS */
-    AR::CpuFunc::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
-    AR::CpuFunc::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
-    AR::CpuFunc::LoadTaskRegister((UINT)KGDT_SYS_TSS);
+    AR::CpuFunctions::LoadGlobalDescriptorTable(&GdtDescriptor.Limit);
+    AR::CpuFunctions::LoadInterruptDescriptorTable(&IdtDescriptor.Limit);
+    AR::CpuFunctions::LoadTaskRegister((UINT)KGDT_SYS_TSS);
 
     /* Initialize segment registers */
     InitializeSegments();
@@ -481,10 +481,10 @@ VOID
 AR::ProcessorSupport::InitializeProcessorRegisters(VOID)
 {
     /* Clear EFLAGS register */
-    AR::CpuFunc::WriteEflagsRegister(0);
+    AR::CpuFunctions::WriteEflagsRegister(0);
 
     /* Enable write-protection */
-    AR::CpuFunc::WriteControlRegister(0, AR::CpuFunc::ReadControlRegister(0) | CR0_WP);
+    AR::CpuFunctions::WriteControlRegister(0, AR::CpuFunctions::ReadControlRegister(0) | CR0_WP);
 }
 
 /**
@@ -585,12 +585,12 @@ VOID
 AR::ProcessorSupport::InitializeSegments(VOID)
 {
     /* Initialize segments */
-    AR::CpuFunc::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
-    AR::CpuFunc::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
-    AR::CpuFunc::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
-    AR::CpuFunc::LoadSegment(SEGMENT_FS, KGDT_R0_PB);
-    AR::CpuFunc::LoadSegment(SEGMENT_GS, 0);
-    AR::CpuFunc::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
+    AR::CpuFunctions::LoadSegment(SEGMENT_CS, KGDT_R0_CODE);
+    AR::CpuFunctions::LoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunctions::LoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
+    AR::CpuFunctions::LoadSegment(SEGMENT_FS, KGDT_R0_PB);
+    AR::CpuFunctions::LoadSegment(SEGMENT_GS, 0);
+    AR::CpuFunctions::LoadSegment(SEGMENT_SS, KGDT_R0_DATA);
 }
 
 /**
@@ -644,7 +644,7 @@ AR::ProcessorSupport::InitializeTss(IN PKPROCESSOR_BLOCK ProcessorBlock,
     ProcessorBlock->TssBase->Flags = 0;
 
     /* Set CR3, LDT and SS */
-    ProcessorBlock->TssBase->CR3 = AR::CpuFunc::ReadControlRegister(3);
+    ProcessorBlock->TssBase->CR3 = AR::CpuFunctions::ReadControlRegister(3);
     ProcessorBlock->TssBase->LDT = 0;
     ProcessorBlock->TssBase->Ss0 = KGDT_R0_DATA;
 
@@ -683,7 +683,7 @@ AR::ProcessorSupport::SetDoubleFaultTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock
     Tss->IoMapBase = sizeof(KTSS);
     Tss->Flags = 0;
     Tss->LDT = 0;
-    Tss->CR3 = AR::CpuFunc::ReadControlRegister(3);
+    Tss->CR3 = AR::CpuFunctions::ReadControlRegister(3);
     Tss->Esp = (ULONG_PTR)KernelFaultStack;
     Tss->Esp0 = (ULONG_PTR)KernelFaultStack;
     Tss->Eip = (ULONG)(ULONG_PTR)ArTrapEntry[0x08];
@@ -897,7 +897,7 @@ AR::ProcessorSupport::SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK Proce
     Tss->IoMapBase = sizeof(KTSS);
     Tss->Flags = 0;
     Tss->LDT = 0;
-    Tss->CR3 = AR::CpuFunc::ReadControlRegister(3);
+    Tss->CR3 = AR::CpuFunctions::ReadControlRegister(3);
     Tss->Esp = (ULONG_PTR)KernelNmiStack;
     Tss->Esp0 = (ULONG_PTR)KernelNmiStack;
     Tss->Eip = (ULONG)(ULONG_PTR)ArTrapEntry[0x02];

xtoskrnl/ar/i686/traps.cc

@@ -26,8 +26,8 @@ AR::Traps::DispatchInterrupt(IN PKTRAP_FRAME TrapFrame)
     PINTERRUPT_HANDLER Handler;
 
     /* Read the handler pointer from the CPU's interrupt dispatch table */
-    Handler = (PINTERRUPT_HANDLER)AR::CpuFunc::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
-                                                              (TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
+    Handler = (PINTERRUPT_HANDLER)AR::CpuFunctions::ReadFSDualWord(FIELD_OFFSET(KPROCESSOR_BLOCK, InterruptDispatchTable) +
+                                                                   (TrapFrame->Vector * sizeof(PINTERRUPT_HANDLER)));
 
     /* Check if the interrupt has a handler registered */
     if(Handler != NULLPTR)