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Rename architecture CPU functions class
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This commit is contained in:
Aiken Harris
2026-05-19 06:45:48 +02:00
parent b03cca65d8
commit 19092eda2e
32 changed files with 271 additions and 270 deletions
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6
xtoskrnl/hl/amd64/irq.cc
View File

@@ -36,7 +36,7 @@ HL::Irq::BeginSystemInterrupt(IN KRUNLEVEL RunLevel,
KE::RunLevel::RaiseRunLevel(RunLevel);
/* Enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/**
@@ -58,7 +58,7 @@ HL::Irq::EndInterrupt(IN PKTRAP_FRAME TrapFrame,
IN KRUNLEVEL OldRunLevel)
{
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* End system interrupt */
EndSystemInterrupt(TrapFrame, OldRunLevel);
@@ -125,7 +125,7 @@ HL::Irq::HandleUnexpectedInterrupt(IN PKTRAP_FRAME TrapFrame)
UNIMPLEMENTED;
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Print debug message and raise kernel panic */
DebugPrint(L"ERROR: Caught unexpected interrupt (0x%.2llX)!\n", TrapFrame->Vector);

4
xtoskrnl/hl/amd64/runlevel.cc
View File

@@ -21,7 +21,7 @@ KRUNLEVEL
HL::RunLevel::GetRunLevel(VOID)
{
/* Read current run level */
return (KRUNLEVEL)AR::CpuFunc::ReadControlRegister(8);
return (KRUNLEVEL)AR::CpuFunctions::ReadControlRegister(8);
}
/**
@@ -39,7 +39,7 @@ VOID
HL::RunLevel::SetRunLevel(IN KRUNLEVEL RunLevel)
{
/* Set new run level */
AR::CpuFunc::WriteControlRegister(8, RunLevel);
AR::CpuFunctions::WriteControlRegister(8, RunLevel);
}
/**

6
xtoskrnl/hl/i686/irq.cc
View File

@@ -37,7 +37,7 @@ HL::Irq::BeginSystemInterrupt(IN KRUNLEVEL RunLevel,
KE::RunLevel::RaiseRunLevel(RunLevel);
/* Enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/**
@@ -59,7 +59,7 @@ HL::Irq::EndInterrupt(IN PKTRAP_FRAME TrapFrame,
IN KRUNLEVEL OldRunLevel)
{
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* End system interrupt */
EndSystemInterrupt(TrapFrame, OldRunLevel);
@@ -126,7 +126,7 @@ HL::Irq::HandleUnexpectedInterrupt(IN PKTRAP_FRAME TrapFrame)
UNIMPLEMENTED;
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Print debug message and raise kernel panic */
DebugPrint(L"ERROR: Caught unexpected interrupt (0x%.2lX)!\n", TrapFrame->Vector);

8
xtoskrnl/hl/x86/cpu.cc
View File

@@ -171,14 +171,14 @@ HL::Cpu::StartAllProcessors(VOID)
KE::Processor::RegisterProcessorBlock(CpuNumber, ProcessorBlock);
/* Initialize processor start block */
StartBlock->Cr3 = AR::CpuFunc::ReadControlRegister(3);
StartBlock->Cr4 = AR::CpuFunc::ReadControlRegister(4);
StartBlock->Cr3 = AR::CpuFunctions::ReadControlRegister(3);
StartBlock->Cr4 = AR::CpuFunctions::ReadControlRegister(4);
StartBlock->EntryPoint = (PVOID)&KE::KernelInit::BootstrapApplicationProcessor;
StartBlock->ProcessorStructures = CpuStructures;
StartBlock->Started = FALSE;
/* Memory barrier */
AR::CpuFunc::MemoryBarrier();
AR::CpuFunctions::MemoryBarrier();
/* Send INIT IPI and wait for 10ms */
HL::Pic::SendIpi(SysInfo->CpuInfo[Index].ApicId, 0, APIC_DM_INIT, APIC_DSH_Destination, APIC_TGM_EDGE);
@@ -196,7 +196,7 @@ HL::Cpu::StartAllProcessors(VOID)
while(!StartBlock->Started && Timeout < 100000)
{
/* Yield processor and wait for 10us */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
HL::Timer::StallExecution(10);
Timeout++;
}

30
xtoskrnl/hl/x86/pic.cc
View File

@@ -364,11 +364,11 @@ HL::Pic::InitializeApic(VOID)
CpuNumber = KE::Processor::GetCurrentProcessorNumber();
/* Enable the APIC */
BaseRegister.LongLong = AR::CpuFunc::ReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
BaseRegister.LongLong = AR::CpuFunctions::ReadModelSpecificRegister(APIC_LAPIC_MSR_BASE);
BaseRegister.Enable = 1;
BaseRegister.ExtendedMode = (ApicMode == APIC_MODE_X2APIC);
BaseRegister.BootStrapProcessor = (CpuNumber == 0) ? 1 : 0;
AR::CpuFunc::WriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
AR::CpuFunctions::WriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong);
/* Mask all interrupts by raising Task Priority Register (TPR) */
WriteApicRegister(APIC_TPR, 0xFF);
@@ -479,8 +479,8 @@ HL::Pic::InitializeIOApic(VOID)
}
/* Perform a memory barrier */
AR::CpuFunc::MemoryBarrier();
AR::CpuFunc::ReadWriteBarrier();
AR::CpuFunctions::MemoryBarrier();
AR::CpuFunctions::ReadWriteBarrier();
/* Read the version register and calculate the maximum number of redirection entries */
VersionRegister = ReadIOApicRegister(&Controllers[ControllerIndex], IOAPIC_VER);
@@ -639,7 +639,7 @@ HL::Pic::ReadApicRegister(IN APIC_REGISTER Register)
if(ApicMode == APIC_MODE_X2APIC)
{
/* Read from x2APIC MSR */
return AR::CpuFunc::ReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
return AR::CpuFunctions::ReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register));
}
else
{
@@ -782,10 +782,10 @@ HL::Pic::SendBroadcastIpi(IN ULONG Vector,
HL::Acpi::GetSystemInformation(&SysInfo);
/* Check whether interrupts are enabled */
Interrupts = AR::CpuFunc::InterruptsEnabled();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Iterate over all logical CPUs */
for(Index = 0; Index < SysInfo->CpuCount; Index++)
@@ -818,7 +818,7 @@ HL::Pic::SendBroadcastIpi(IN ULONG Vector,
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
}
@@ -871,10 +871,10 @@ HL::Pic::SendIpi(IN ULONG ApicId,
BOOLEAN Interrupts;
/* Check whether interrupts are enabled */
Interrupts = AR::CpuFunc::InterruptsEnabled();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Check current APIC mode and destination */
if(ApicMode == APIC_MODE_X2APIC && DestinationShortHand == APIC_DSH_Self)
@@ -886,7 +886,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
if(Interrupts)
{
/* Check whether interrupts need to be re-enabled */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/* Nothing more to do */
@@ -917,7 +917,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
while((ReadApicRegister(APIC_ICR0) & 0x1000) != 0)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
/* In xAPIC compatibility mode, write the command to the ICR registers */
@@ -931,7 +931,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
while((ReadApicRegister((APIC_REGISTER)(APIC_IRR + (Vector / 32))) & (1UL << (Vector % 32))) == 0)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}
}
@@ -940,7 +940,7 @@ HL::Pic::SendIpi(IN ULONG ApicId,
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
}
@@ -1016,7 +1016,7 @@ HL::Pic::WriteApicRegister(IN APIC_REGISTER Register,
if(ApicMode == APIC_MODE_X2APIC)
{
/* Write to x2APIC MSR */
AR::CpuFunc::WriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
AR::CpuFunctions::WriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value);
}
else
{

4
xtoskrnl/hl/x86/rtc.cc
View File

@@ -58,7 +58,7 @@ HL::Rtc::GetRealTimeClock(OUT PTIME_FIELDS Time)
while(HL::Firmware::ReadCmosRegister(CMOS_REGISTER_A) & CMOS_REGISTER_A_UPDATE_IN_PROGRESS)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
/* Latch the first sequential hardware time snapshot */
@@ -81,7 +81,7 @@ HL::Rtc::GetRealTimeClock(OUT PTIME_FIELDS Time)
while(HL::Firmware::ReadCmosRegister(CMOS_REGISTER_A) & CMOS_REGISTER_A_UPDATE_IN_PROGRESS)
{
/* Yield the processor */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
/* Latch the second sequential hardware time snapshot for verification */

26
xtoskrnl/hl/x86/timer.cc
View File

@@ -84,13 +84,13 @@ HL::Timer::CalibrateTscCounter(VOID)
}
/* Latch the initial TSC value */
InitialTickCount = AR::CpuFunc::ReadTimeStampCounterProcessor(&TscAux);
InitialTickCount = AR::CpuFunctions::ReadTimeStampCounterProcessor(&TscAux);
/* Stall CPU execution for exactly 10 milliseconds */
StallExecution(10000);
/* Read current tick count from TSC */
FinalTickCount = AR::CpuFunc::ReadTimeStampCounterProcessor(&TscAux);
FinalTickCount = AR::CpuFunctions::ReadTimeStampCounterProcessor(&TscAux);
/* Calculate the elapsed ticks over the 10ms window */
return (FinalTickCount - InitialTickCount) * 100;
@@ -915,7 +915,7 @@ HL::Timer::QueryPerformanceCounterTsc(VOID)
ULONG TscAux;
/* Retrieve the timestamp */
return AR::CpuFunc::ReadTimeStampCounterProcessor(&TscAux);
return AR::CpuFunctions::ReadTimeStampCounterProcessor(&TscAux);
}
/**
@@ -945,7 +945,7 @@ HL::Timer::QueryTimerCapabilities(VOID)
/* Query maximum standard CPUID leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_VENDOR_STRING;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
MaxStandardLeaf = CpuRegisters.Eax;
/* Check Always Running Timer - ART if leaf supported */
@@ -954,7 +954,7 @@ HL::Timer::QueryTimerCapabilities(VOID)
/* Query the Time Stamp Counter and Core Crystal Clock information CPUID leaf */
RTL::Memory::ZeroMemory(&CpuRegisters, sizeof(CPUID_REGISTERS));
CpuRegisters.Leaf = CPUID_GET_TSC_CRYSTAL_CLOCK;
AR::CpuFunc::CpuId(&CpuRegisters);
AR::CpuFunctions::CpuId(&CpuRegisters);
/* Verify Always Running Timer support */
if(CpuRegisters.Eax != 0 && CpuRegisters.Ebx != 0)
@@ -1051,10 +1051,10 @@ HL::Timer::SetClockRateApic(ULONG Rate)
}
/* Check whether interrupts are enabled */
Interrupts = AR::CpuFunc::InterruptsEnabled();
Interrupts = AR::CpuFunctions::InterruptsEnabled();
/* Disable interrupts */
AR::CpuFunc::ClearInterruptFlag();
AR::CpuFunctions::ClearInterruptFlag();
/* Commit the new divider to the TICR register */
HL::Pic::WriteApicRegister(APIC_TICR, NewDivider);
@@ -1066,7 +1066,7 @@ HL::Timer::SetClockRateApic(ULONG Rate)
if(Interrupts)
{
/* Re-enable interrupts */
AR::CpuFunc::SetInterruptFlag();
AR::CpuFunctions::SetInterruptFlag();
}
/* Return the actual clock rate set */
@@ -1178,7 +1178,7 @@ HL::Timer::StallExecutionAcpiPm(IN ULONG MicroSeconds)
StartTick = CurrentTick;
/* Issue a PAUSE instruction to relieve memory bus contention */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}
@@ -1222,7 +1222,7 @@ HL::Timer::StallExecutionHpet(IN ULONG MicroSeconds)
while((Hpet->MainCounterValue - StartTick) < TargetTicks)
{
/* Issue a PAUSE instruction to relieve memory bus contention */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}
@@ -1327,13 +1327,13 @@ HL::Timer::StallExecutionTsc(IN ULONG MicroSeconds)
/* Calculate target ticks based on calibrated TSC frequency */
TargetTicks = ((ULONGLONG)MicroSeconds * PerformanceFrequency) / 1000000ULL;
StartTick = AR::CpuFunc::ReadTimeStampCounter();
StartTick = AR::CpuFunctions::ReadTimeStampCounter();
/* Spin until the elapsed ticks reach the target */
while((AR::CpuFunc::ReadTimeStampCounter() - StartTick) < TargetTicks)
while((AR::CpuFunctions::ReadTimeStampCounter() - StartTick) < TargetTicks)
{
/* Issue a PAUSE instruction to relieve memory bus contention */
AR::CpuFunc::YieldProcessor();
AR::CpuFunctions::YieldProcessor();
}
}