Rename architecture CPU functions class

xtoskrnl/mm/amd64/paging.cc

@@ -22,7 +22,7 @@ BOOLEAN
 MM::Paging::GetExtendedPhysicalAddressingStatus(VOID)
 {
     /* Check if LA57 is enabled */
-    return ((AR::CpuFunc::ReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
+    return ((AR::CpuFunctions::ReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
 }
 
 /**

xtoskrnl/mm/amd64/pte.cc

@@ -99,7 +99,7 @@ MM::Pte::InitializePageTable(VOID)
     MemoryLayout = MM::Manager::GetMemoryLayout();
 
     /* Enable the Global Paging (PGE) feature */
-    AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PGE);
+    AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_PGE);
 
     /* Check XPA status */
     if(Xpa)
@@ -123,7 +123,7 @@ MM::Pte::InitializePageTable(VOID)
     }
 
     /* Flush the TLB to invalidate all non-global entries */
-    AR::CpuFunc::FlushTlb();
+    AR::CpuFunctions::FlushTlb();
 
     /* Create a template PTE for mapping kernel pages */
     MM::Paging::ClearPte(&TemplatePte);

xtoskrnl/mm/i686/paging.cc

@@ -22,7 +22,7 @@ BOOLEAN
 MM::Paging::GetExtendedPhysicalAddressingStatus(VOID)
 {
     /* Check if PAE is enabled */
-    return ((AR::CpuFunc::ReadControlRegister(4) & CR4_PAE) != 0) ? TRUE : FALSE;
+    return ((AR::CpuFunctions::ReadControlRegister(4) & CR4_PAE) != 0) ? TRUE : FALSE;
 }
 
 /**

xtoskrnl/mm/i686/pfn.cc

@@ -150,7 +150,7 @@ MM::Pfn::InitializePageTablePfns(VOID)
         RootLevel = 3;
 
         /* Retrieve the PFN of the PML3 table and its virtual base address */
-        PageFrameIndex = AR::CpuFunc::ReadControlRegister(3) >> MM_PAGE_SHIFT;
+        PageFrameIndex = AR::CpuFunctions::ReadControlRegister(3) >> MM_PAGE_SHIFT;
         RootPte = (PMMPTE)MM::Paging::GetPpeAddress(NULLPTR);
     }
     else
@@ -159,7 +159,7 @@ MM::Pfn::InitializePageTablePfns(VOID)
         RootLevel = 2;
 
         /* Retrieve the PFN of the PML2 table and its virtual base address */
-        PageFrameIndex = AR::CpuFunc::ReadControlRegister(3) >> MM_PAGE_SHIFT;
+        PageFrameIndex = AR::CpuFunctions::ReadControlRegister(3) >> MM_PAGE_SHIFT;
         RootPte = (PMMPTE)MM::Paging::GetPdeAddress(NULLPTR);
     }
 

xtoskrnl/mm/i686/pte.cc

@@ -70,13 +70,13 @@ MM::Pte::InitializePageTable(VOID)
 
     /* Get CPU features */
     CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
 
     /* Check if Paging Global Extensions (PGE) is supported */
     if(CpuRegisters.Edx & CPUID_FEATURES_EDX_PGE)
     {
         /* Enable the Global Paging (PGE) feature */
-        AR::CpuFunc::WriteControlRegister(4, AR::CpuFunc::ReadControlRegister(4) | CR4_PGE);
+        AR::CpuFunctions::WriteControlRegister(4, AR::CpuFunctions::ReadControlRegister(4) | CR4_PGE);
     }
 
     /* Get the PD user-space range for both legacy and PAE paging */
@@ -91,7 +91,7 @@ MM::Pte::InitializePageTable(VOID)
     }
 
     /* Flush the TLB to invalidate all non-global entries */
-    AR::CpuFunc::FlushTlb();
+    AR::CpuFunctions::FlushTlb();
 
     /* Create a template PTE for mapping kernel pages */
     MM::Paging::ClearPte(&TemplatePte);

xtoskrnl/mm/mmgr.cc

@@ -279,7 +279,7 @@ MM::Manager::InitializeMemoryManager(VOID)
     MM::Pool::InitializePagedPool();
 
     /* Flush TLB */
-    AR::CpuFunc::FlushTlb();
+    AR::CpuFunctions::FlushTlb();
 }
 
 /**

xtoskrnl/mm/paging.cc

@@ -98,39 +98,39 @@ MM::Paging::FlushTlb(VOID)
     ULONG_PTR Cr4;
 
     /* Save interrupts state and disable them */
-    Interrupts = AR::CpuFunc::InterruptsEnabled();
-    AR::CpuFunc::ClearInterruptFlag();
+    Interrupts = AR::CpuFunctions::InterruptsEnabled();
+    AR::CpuFunctions::ClearInterruptFlag();
 
     /* Get CPU features */
     CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
-    AR::CpuFunc::CpuId(&CpuRegisters);
+    AR::CpuFunctions::CpuId(&CpuRegisters);
 
     /* Check if Paging Global Extensions (PGE) is supported */
     if(CpuRegisters.Edx & CPUID_FEATURES_EDX_PGE)
     {
         /* Read CR4 */
-        Cr4 = AR::CpuFunc::ReadControlRegister(4);
+        Cr4 = AR::CpuFunctions::ReadControlRegister(4);
 
         /* Disable PGE */
-        AR::CpuFunc::WriteControlRegister(4, Cr4 & ~CR4_PGE);
+        AR::CpuFunctions::WriteControlRegister(4, Cr4 & ~CR4_PGE);
 
         /* Flush the TLB */
-        AR::CpuFunc::FlushTlb();
+        AR::CpuFunctions::FlushTlb();
 
         /* Restore CR4 */
-        AR::CpuFunc::WriteControlRegister(4, Cr4);
+        AR::CpuFunctions::WriteControlRegister(4, Cr4);
     }
     else
     {
         /* Simply flush the TLB */
-        AR::CpuFunc::FlushTlb();
+        AR::CpuFunctions::FlushTlb();
     }
 
     /* Check if interrupts should be enabled */
     if(Interrupts)
     {
         /* Re-enable interrupts */
-        AR::CpuFunc::SetInterruptFlag();
+        AR::CpuFunctions::SetInterruptFlag();
     }
 }
 

xtoskrnl/mm/pte.cc

@@ -539,7 +539,7 @@ MM::Pte::ReserveSystemPtes(IN PFN_COUNT NumberOfPtes,
     TotalSystemFreePtes[SystemPtePoolType] -= NumberOfPtes;
 
     /* Flush the TLB to ensure address translation consistency */
-    AR::CpuFunc::FlushTlb();
+    AR::CpuFunctions::FlushTlb();
 
     /* Return a pointer to the start of the reserved PTE block */
     return ReservedPte;