Add trampoline to enable 5-level paging
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@@ -10,6 +10,21 @@
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#define __XTOSKRNL_AMD64_ASMSUP_H
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/* Control Register bit definitions */
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#define CR0_PG 0x80000000
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#define CR4_PGE 0x00000080
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#define CR4_LA57 0x00001000
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#define CR4_PCIDE 0x00020000
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/* GDT selectors */
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#define GDT_R0_CMCODE 0x08
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#define GDT_R0_CODE 0x10
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#define GDT_R0_DATA 0x18
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/* MSR registers */
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#define X86_MSR_EFER 0xC0000080
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#define X86_MSR_EFER_LME (1 << 8)
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/* KTRAP_FRAME structure offsets */
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#define TrapXmm0 0
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#define TrapXmm1 16
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