From 27e2fdf4f2e2b3780b8712a71c47c6c34bc3ef5d Mon Sep 17 00:00:00 2001 From: belliash Date: Sat, 28 Jan 2023 10:34:55 +0100 Subject: [PATCH] Introduce architecture library as new kernel subsystem and move selected routines into new subsystem --- sdk/xtdk/amd64/arfuncs.h | 99 ++++++++++++++++ sdk/xtdk/amd64/artypes.h | 146 +++++++++++++++++++++++ sdk/xtdk/amd64/hlfuncs.h | 80 ------------- sdk/xtdk/amd64/hltypes.h | 126 -------------------- sdk/xtdk/i686/arfuncs.h | 95 +++++++++++++++ sdk/xtdk/i686/artypes.h | 146 +++++++++++++++++++++++ sdk/xtdk/i686/hlfuncs.h | 76 ------------ sdk/xtdk/i686/hltypes.h | 126 -------------------- sdk/xtdk/xtkmapi.h | 2 + xtldr/amd64/memory.c | 2 +- xtldr/i686/memory.c | 8 +- xtldr/modules/xtos/amd64/cpu.c | 10 +- xtldr/modules/xtos/i686/cpu.c | 12 +- xtldr/xtldr.c | 4 +- xtoskrnl/CMakeLists.txt | 3 +- xtoskrnl/{hl => ar}/amd64/cpufunc.c | 175 ++++------------------------ xtoskrnl/{hl => ar}/i686/cpufunc.c | 173 +++------------------------ xtoskrnl/hl/amd64/ioport.c | 145 +++++++++++++++++++++++ xtoskrnl/hl/i686/ioport.c | 145 +++++++++++++++++++++++ 19 files changed, 837 insertions(+), 736 deletions(-) create mode 100644 sdk/xtdk/amd64/arfuncs.h create mode 100644 sdk/xtdk/amd64/artypes.h create mode 100644 sdk/xtdk/i686/arfuncs.h create mode 100644 sdk/xtdk/i686/artypes.h rename xtoskrnl/{hl => ar}/amd64/cpufunc.c (78%) rename xtoskrnl/{hl => ar}/i686/cpufunc.c (76%) create mode 100644 xtoskrnl/hl/amd64/ioport.c create mode 100644 xtoskrnl/hl/i686/ioport.c diff --git a/sdk/xtdk/amd64/arfuncs.h b/sdk/xtdk/amd64/arfuncs.h new file mode 100644 index 0000000..12b8f88 --- /dev/null +++ b/sdk/xtdk/amd64/arfuncs.h @@ -0,0 +1,99 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: sdk/xtdk/amd64/arfuncs.h + * DESCRIPTION: AMD64 architecture library routines + * DEVELOPERS: Rafal Kupiec + */ + +#ifndef __XTDK_AMD64_ARFUNCS_H +#define __XTDK_AMD64_ARFUNCS_H + +#include +#include +#include +#include + + +/* Architecture library routines forward references */ +XTCDECL +VOID +ArClearInterruptFlag(); + +XTCDECL +BOOLEAN +ArCpuId(IN OUT PCPUID_REGISTERS Registers); + +XTCDECL +VOID +ArHalt(); + +XTCDECL +VOID +ArInvalidateTlbEntry(IN PVOID Address); + +XTCDECL +VOID +ArLoadGlobalDescriptorTable(IN PVOID Source); + +XTCDECL +VOID +ArLoadInterruptDescriptorTable(IN PVOID Source); + +XTCDECL +VOID +ArLoadSegment(IN USHORT Segment, + IN ULONG Source); + +XTCDECL +VOID +ArLoadTaskRegister(USHORT Source); + +XTCDECL +ULONG_PTR +ArReadControlRegister(IN USHORT ControlRegister); + +XTCDECL +ULONGLONG +ArReadGSQuadWord(ULONG Offset); + +XTCDECL +ULONGLONG +ArReadModelSpecificRegister(IN ULONG Register); + +XTCDECL +ULONGLONG +ArReadTimeStampCounter(); + +XTCDECL +VOID +ArSetInterruptFlag(); + +XTCDECL +VOID +ArStoreGlobalDescriptorTable(OUT PVOID Destination); + +XTCDECL +VOID +ArStoreInterruptDescriptorTable(OUT PVOID Destination); + +XTCDECL +VOID +ArStoreSegment(IN USHORT Segment, + OUT PVOID Destination); + +XTCDECL +VOID +ArStoreTaskRegister(OUT PVOID Destination); + +XTCDECL +VOID +ArWriteControlRegister(IN USHORT ControlRegister, + IN UINT_PTR Value); + +XTCDECL +VOID +ArWriteModelSpecificRegister(IN ULONG Register, + IN ULONGLONG Value); + +#endif /* __XTDK_AMD64_ARFUNCS_H */ diff --git a/sdk/xtdk/amd64/artypes.h b/sdk/xtdk/amd64/artypes.h new file mode 100644 index 0000000..ebb81b0 --- /dev/null +++ b/sdk/xtdk/amd64/artypes.h @@ -0,0 +1,146 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: sdk/xtdk/amd64/artypes.h + * DESCRIPTION: AMD64 architecture library structure definitions + * DEVELOPERS: Rafal Kupiec + */ + +#ifndef __XTDK_AMD64_ARTYPES_H +#define __XTDK_AMD64_ARTYPES_H + +#include +#include +#include + + +/* Control Register 0 constants */ +#define CR0_PE 0x00000001 +#define CR0_MP 0x00000002 +#define CR0_EM 0x00000004 +#define CR0_TS 0x00000008 +#define CR0_ET 0x00000010 +#define CR0_NE 0x00000020 +#define CR0_WP 0x00010000 +#define CR0_AM 0x00040000 +#define CR0_NW 0x20000000 +#define CR0_CD 0x40000000 +#define CR0_PG 0x80000000 + +/* Control Register 4 constants */ +#define CR4_VME 0x00000001 +#define CR4_PVI 0x00000002 +#define CR4_TSD 0x00000004 +#define CR4_DE 0x00000008 +#define CR4_PSE 0x00000010 +#define CR4_PAE 0x00000020 +#define CR4_MCE 0x00000040 +#define CR4_PGE 0x00000080 +#define CR4_PCE 0x00000100 +#define CR4_FXSR 0x00000200 +#define CR4_XMMEXCPT 0x00000400 +#define CR4_RESERVED1 0x00001800 +#define CR4_VMXE 0x00002000 +#define CR4_SMXE 0x00004000 +#define CR4_RESERVED2 0x00018000 +#define CR4_XSAVE 0x00020000 +#define CR4_RESERVED3 0xFFFC0000 + +/* Initial MXCSR control */ +#define INITIAL_MXCSR 0x1F80 + +/* Segment defintions */ +#define SEGMENT_CS 0x2E +#define SEGMENT_DS 0x3E +#define SEGMENT_ES 0x26 +#define SEGMENT_SS 0x36 +#define SEGMENT_FS 0x64 +#define SEGMENT_GS 0x65 + +/* CPUID features enumeration list */ +typedef enum _CPUID_FEATURES +{ + CPUID_FEATURES_ECX_SSE3 = 1 << 0, + CPUID_FEATURES_ECX_PCLMUL = 1 << 1, + CPUID_FEATURES_ECX_DTES64 = 1 << 2, + CPUID_FEATURES_ECX_MONITOR = 1 << 3, + CPUID_FEATURES_ECX_DS_CPL = 1 << 4, + CPUID_FEATURES_ECX_VMX = 1 << 5, + CPUID_FEATURES_ECX_SMX = 1 << 6, + CPUID_FEATURES_ECX_EST = 1 << 7, + CPUID_FEATURES_ECX_TM2 = 1 << 8, + CPUID_FEATURES_ECX_SSSE3 = 1 << 9, + CPUID_FEATURES_ECX_CID = 1 << 10, + CPUID_FEATURES_ECX_SDBG = 1 << 11, + CPUID_FEATURES_ECX_FMA = 1 << 12, + CPUID_FEATURES_ECX_CX16 = 1 << 13, + CPUID_FEATURES_ECX_XTPR = 1 << 14, + CPUID_FEATURES_ECX_PDCM = 1 << 15, + CPUID_FEATURES_ECX_PCID = 1 << 17, + CPUID_FEATURES_ECX_DCA = 1 << 18, + CPUID_FEATURES_ECX_SSE4_1 = 1 << 19, + CPUID_FEATURES_ECX_SSE4_2 = 1 << 20, + CPUID_FEATURES_ECX_X2APIC = 1 << 21, + CPUID_FEATURES_ECX_MOVBE = 1 << 22, + CPUID_FEATURES_ECX_POPCNT = 1 << 23, + CPUID_FEATURES_ECX_TSC = 1 << 24, + CPUID_FEATURES_ECX_AES = 1 << 25, + CPUID_FEATURES_ECX_XSAVE = 1 << 26, + CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, + CPUID_FEATURES_ECX_AVX = 1 << 28, + CPUID_FEATURES_ECX_F16C = 1 << 29, + CPUID_FEATURES_ECX_RDRAND = 1 << 30, + CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31, + CPUID_FEATURES_EDX_FPU = 1 << 0, + CPUID_FEATURES_EDX_VME = 1 << 1, + CPUID_FEATURES_EDX_DE = 1 << 2, + CPUID_FEATURES_EDX_PSE = 1 << 3, + CPUID_FEATURES_EDX_TSC = 1 << 4, + CPUID_FEATURES_EDX_MSR = 1 << 5, + CPUID_FEATURES_EDX_PAE = 1 << 6, + CPUID_FEATURES_EDX_MCE = 1 << 7, + CPUID_FEATURES_EDX_CX8 = 1 << 8, + CPUID_FEATURES_EDX_APIC = 1 << 9, + CPUID_FEATURES_EDX_SEP = 1 << 11, + CPUID_FEATURES_EDX_MTRR = 1 << 12, + CPUID_FEATURES_EDX_PGE = 1 << 13, + CPUID_FEATURES_EDX_MCA = 1 << 14, + CPUID_FEATURES_EDX_CMOV = 1 << 15, + CPUID_FEATURES_EDX_PAT = 1 << 16, + CPUID_FEATURES_EDX_PSE36 = 1 << 17, + CPUID_FEATURES_EDX_PSN = 1 << 18, + CPUID_FEATURES_EDX_CLFLUSH = 1 << 19, + CPUID_FEATURES_EDX_DS = 1 << 21, + CPUID_FEATURES_EDX_ACPI = 1 << 22, + CPUID_FEATURES_EDX_MMX = 1 << 23, + CPUID_FEATURES_EDX_FXSR = 1 << 24, + CPUID_FEATURES_EDX_SSE = 1 << 25, + CPUID_FEATURES_EDX_SSE2 = 1 << 26, + CPUID_FEATURES_EDX_SS = 1 << 27, + CPUID_FEATURES_EDX_HTT = 1 << 28, + CPUID_FEATURES_EDX_TM = 1 << 29, + CPUID_FEATURES_EDX_IA64 = 1 << 30, + CPUID_FEATURES_EDX_PBE = 1 << 31 +} CPUID_FEATURES, *PCPUID_FEATURES; + +/* CPUID requests */ +typedef enum _CPUID_REQUESTS +{ + CPUID_GET_VENDOR_STRING, + CPUID_GET_CPU_FEATURES, + CPUID_GET_TLB, + CPUID_GET_SERIAL +} CPUID_REQUESTS, *PCPUID_REQUESTS; + +/* CPUID registers */ +typedef struct _CPUID_REGISTERS +{ + UINT32 Leaf; + UINT32 SubLeaf; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; +} CPUID_REGISTERS, *PCPUID_REGISTERS; + +#endif /* __XTDK_AMD64_ARTYPES_H */ diff --git a/sdk/xtdk/amd64/hlfuncs.h b/sdk/xtdk/amd64/hlfuncs.h index 6c453e6..925cf74 100644 --- a/sdk/xtdk/amd64/hlfuncs.h +++ b/sdk/xtdk/amd64/hlfuncs.h @@ -16,22 +16,6 @@ /* HAL library routines forward references */ -XTCDECL -VOID -HlClearInterruptFlag(); - -XTCDECL -BOOLEAN -HlCpuId(IN OUT PCPUID_REGISTERS Registers); - -XTCDECL -VOID -HlHalt(); - -XTCDECL -VOID -HlInvalidateTlbEntry(IN PVOID Address); - XTCDECL UCHAR HlIoPortInByte(IN USHORT Port); @@ -59,68 +43,4 @@ VOID HlIoPortOutLong(IN USHORT Port, IN ULONG Value); -XTCDECL -VOID -HlLoadGlobalDescriptorTable(IN PVOID Source); - -XTCDECL -VOID -HlLoadInterruptDescriptorTable(IN PVOID Source); - -XTCDECL -VOID -HlLoadSegment(IN USHORT Segment, - IN ULONG Source); - -XTCDECL -VOID -HlLoadTaskRegister(USHORT Source); - -XTCDECL -ULONG_PTR -HlReadControlRegister(IN USHORT ControlRegister); - -XTCDECL -ULONGLONG -HlReadGSQuadWord(ULONG Offset); - -XTCDECL -ULONGLONG -HlReadModelSpecificRegister(IN ULONG Register); - -XTCDECL -ULONGLONG -HlReadTimeStampCounter(); - -XTCDECL -VOID -HlSetInterruptFlag(); - -XTCDECL -VOID -HlStoreGlobalDescriptorTable(OUT PVOID Destination); - -XTCDECL -VOID -HlStoreInterruptDescriptorTable(OUT PVOID Destination); - -XTCDECL -VOID -HlStoreSegment(IN USHORT Segment, - OUT PVOID Destination); - -XTCDECL -VOID -HlStoreTaskRegister(OUT PVOID Destination); - -XTCDECL -VOID -HlWriteControlRegister(IN USHORT ControlRegister, - IN UINT_PTR Value); - -XTCDECL -VOID -HlWriteModelSpecificRegister(IN ULONG Register, - IN ULONGLONG Value); - #endif /* __XTDK_AMD64_HLFUNCS_H */ diff --git a/sdk/xtdk/amd64/hltypes.h b/sdk/xtdk/amd64/hltypes.h index b504f6d..33926fe 100644 --- a/sdk/xtdk/amd64/hltypes.h +++ b/sdk/xtdk/amd64/hltypes.h @@ -17,130 +17,4 @@ /* Serial port I/O addresses */ #define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8} -/* Control Register 0 constants */ -#define CR0_PE 0x00000001 -#define CR0_MP 0x00000002 -#define CR0_EM 0x00000004 -#define CR0_TS 0x00000008 -#define CR0_ET 0x00000010 -#define CR0_NE 0x00000020 -#define CR0_WP 0x00010000 -#define CR0_AM 0x00040000 -#define CR0_NW 0x20000000 -#define CR0_CD 0x40000000 -#define CR0_PG 0x80000000 - -/* Control Register 4 constants */ -#define CR4_VME 0x00000001 -#define CR4_PVI 0x00000002 -#define CR4_TSD 0x00000004 -#define CR4_DE 0x00000008 -#define CR4_PSE 0x00000010 -#define CR4_PAE 0x00000020 -#define CR4_MCE 0x00000040 -#define CR4_PGE 0x00000080 -#define CR4_PCE 0x00000100 -#define CR4_FXSR 0x00000200 -#define CR4_XMMEXCPT 0x00000400 -#define CR4_RESERVED1 0x00001800 -#define CR4_VMXE 0x00002000 -#define CR4_SMXE 0x00004000 -#define CR4_RESERVED2 0x00018000 -#define CR4_XSAVE 0x00020000 -#define CR4_RESERVED3 0xFFFC0000 - -/* Segment defintions */ -#define SEGMENT_CS 0x2E -#define SEGMENT_DS 0x3E -#define SEGMENT_ES 0x26 -#define SEGMENT_SS 0x36 -#define SEGMENT_FS 0x64 -#define SEGMENT_GS 0x65 - -/* CPUID features enumeration list */ -typedef enum _CPUID_FEATURES -{ - CPUID_FEATURES_ECX_SSE3 = 1 << 0, - CPUID_FEATURES_ECX_PCLMUL = 1 << 1, - CPUID_FEATURES_ECX_DTES64 = 1 << 2, - CPUID_FEATURES_ECX_MONITOR = 1 << 3, - CPUID_FEATURES_ECX_DS_CPL = 1 << 4, - CPUID_FEATURES_ECX_VMX = 1 << 5, - CPUID_FEATURES_ECX_SMX = 1 << 6, - CPUID_FEATURES_ECX_EST = 1 << 7, - CPUID_FEATURES_ECX_TM2 = 1 << 8, - CPUID_FEATURES_ECX_SSSE3 = 1 << 9, - CPUID_FEATURES_ECX_CID = 1 << 10, - CPUID_FEATURES_ECX_SDBG = 1 << 11, - CPUID_FEATURES_ECX_FMA = 1 << 12, - CPUID_FEATURES_ECX_CX16 = 1 << 13, - CPUID_FEATURES_ECX_XTPR = 1 << 14, - CPUID_FEATURES_ECX_PDCM = 1 << 15, - CPUID_FEATURES_ECX_PCID = 1 << 17, - CPUID_FEATURES_ECX_DCA = 1 << 18, - CPUID_FEATURES_ECX_SSE4_1 = 1 << 19, - CPUID_FEATURES_ECX_SSE4_2 = 1 << 20, - CPUID_FEATURES_ECX_X2APIC = 1 << 21, - CPUID_FEATURES_ECX_MOVBE = 1 << 22, - CPUID_FEATURES_ECX_POPCNT = 1 << 23, - CPUID_FEATURES_ECX_TSC = 1 << 24, - CPUID_FEATURES_ECX_AES = 1 << 25, - CPUID_FEATURES_ECX_XSAVE = 1 << 26, - CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, - CPUID_FEATURES_ECX_AVX = 1 << 28, - CPUID_FEATURES_ECX_F16C = 1 << 29, - CPUID_FEATURES_ECX_RDRAND = 1 << 30, - CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31, - CPUID_FEATURES_EDX_FPU = 1 << 0, - CPUID_FEATURES_EDX_VME = 1 << 1, - CPUID_FEATURES_EDX_DE = 1 << 2, - CPUID_FEATURES_EDX_PSE = 1 << 3, - CPUID_FEATURES_EDX_TSC = 1 << 4, - CPUID_FEATURES_EDX_MSR = 1 << 5, - CPUID_FEATURES_EDX_PAE = 1 << 6, - CPUID_FEATURES_EDX_MCE = 1 << 7, - CPUID_FEATURES_EDX_CX8 = 1 << 8, - CPUID_FEATURES_EDX_APIC = 1 << 9, - CPUID_FEATURES_EDX_SEP = 1 << 11, - CPUID_FEATURES_EDX_MTRR = 1 << 12, - CPUID_FEATURES_EDX_PGE = 1 << 13, - CPUID_FEATURES_EDX_MCA = 1 << 14, - CPUID_FEATURES_EDX_CMOV = 1 << 15, - CPUID_FEATURES_EDX_PAT = 1 << 16, - CPUID_FEATURES_EDX_PSE36 = 1 << 17, - CPUID_FEATURES_EDX_PSN = 1 << 18, - CPUID_FEATURES_EDX_CLFLUSH = 1 << 19, - CPUID_FEATURES_EDX_DS = 1 << 21, - CPUID_FEATURES_EDX_ACPI = 1 << 22, - CPUID_FEATURES_EDX_MMX = 1 << 23, - CPUID_FEATURES_EDX_FXSR = 1 << 24, - CPUID_FEATURES_EDX_SSE = 1 << 25, - CPUID_FEATURES_EDX_SSE2 = 1 << 26, - CPUID_FEATURES_EDX_SS = 1 << 27, - CPUID_FEATURES_EDX_HTT = 1 << 28, - CPUID_FEATURES_EDX_TM = 1 << 29, - CPUID_FEATURES_EDX_IA64 = 1 << 30, - CPUID_FEATURES_EDX_PBE = 1 << 31 -} CPUID_FEATURES, *PCPUID_FEATURES; - -/* CPUID requests */ -typedef enum _CPUID_REQUESTS -{ - CPUID_GET_VENDOR_STRING, - CPUID_GET_CPU_FEATURES, - CPUID_GET_TLB, - CPUID_GET_SERIAL -} CPUID_REQUESTS, *PCPUID_REQUESTS; - -/* CPUID registers */ -typedef struct _CPUID_REGISTERS -{ - UINT32 Leaf; - UINT32 SubLeaf; - UINT32 Eax; - UINT32 Ebx; - UINT32 Ecx; - UINT32 Edx; -} CPUID_REGISTERS, *PCPUID_REGISTERS; - #endif /* __XTDK_AMD64_HLTYPES_H */ diff --git a/sdk/xtdk/i686/arfuncs.h b/sdk/xtdk/i686/arfuncs.h new file mode 100644 index 0000000..6a9140f --- /dev/null +++ b/sdk/xtdk/i686/arfuncs.h @@ -0,0 +1,95 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: sdk/xtdk/i686/arfuncs.h + * DESCRIPTION: I686 architecture library routines + * DEVELOPERS: Rafal Kupiec + */ + +#ifndef __XTDK_I686_ARFUNCS_H +#define __XTDK_I686_ARFUNCS_H + +#include +#include +#include +#include + + +/* Architecture library routines forward references */ +XTCDECL +VOID +ArClearInterruptFlag(); + +XTCDECL +BOOLEAN +ArCpuId(IN OUT PCPUID_REGISTERS Registers); + +XTCDECL +VOID +ArHalt(); + +XTCDECL +VOID +ArInvalidateTlbEntry(IN PVOID Address); + +XTCDECL +VOID +ArLoadGlobalDescriptorTable(IN PVOID Source); + +XTCDECL +VOID +ArLoadInterruptDescriptorTable(IN PVOID Source); + +XTCDECL +VOID +ArLoadSegment(IN USHORT Segment, + IN ULONG Source); + +XTCDECL +VOID +ArLoadTaskRegister(USHORT Source); + +XTCDECL +ULONG_PTR +ArReadControlRegister(IN USHORT ControlRegister); + +XTCDECL +ULONGLONG +ArReadModelSpecificRegister(IN ULONG Register); + +XTCDECL +ULONGLONG +ArReadTimeStampCounter(); + +XTCDECL +VOID +ArSetInterruptFlag(); + +XTCDECL +VOID +ArStoreGlobalDescriptorTable(OUT PVOID Destination); + +XTCDECL +VOID +ArStoreInterruptDescriptorTable(OUT PVOID Destination); + +XTCDECL +VOID +ArStoreSegment(IN USHORT Segment, + OUT PVOID Destination); + +XTCDECL +VOID +ArStoreTaskRegister(OUT PVOID Destination); + +XTCDECL +VOID +ArWriteControlRegister(IN USHORT ControlRegister, + IN UINT_PTR Value); + +XTCDECL +VOID +ArWriteModelSpecificRegister(IN ULONG Register, + IN ULONGLONG Value); + +#endif /* __XTDK_I686_ARFUNCS_H */ diff --git a/sdk/xtdk/i686/artypes.h b/sdk/xtdk/i686/artypes.h new file mode 100644 index 0000000..96bc2fd --- /dev/null +++ b/sdk/xtdk/i686/artypes.h @@ -0,0 +1,146 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: sdk/xtdk/i686/artypes.h + * DESCRIPTION: I686 architecture library structure definitions + * DEVELOPERS: Rafal Kupiec + */ + +#ifndef __XTDK_I686_ARTYPES_H +#define __XTDK_I686_ARTYPES_H + +#include +#include +#include + + +/* Control Register 0 constants */ +#define CR0_PE 0x00000001 +#define CR0_MP 0x00000002 +#define CR0_EM 0x00000004 +#define CR0_TS 0x00000008 +#define CR0_ET 0x00000010 +#define CR0_NE 0x00000020 +#define CR0_WP 0x00010000 +#define CR0_AM 0x00040000 +#define CR0_NW 0x20000000 +#define CR0_CD 0x40000000 +#define CR0_PG 0x80000000 + +/* Control Register 4 constants */ +#define CR4_VME 0x00000001 +#define CR4_PVI 0x00000002 +#define CR4_TSD 0x00000004 +#define CR4_DE 0x00000008 +#define CR4_PSE 0x00000010 +#define CR4_PAE 0x00000020 +#define CR4_MCE 0x00000040 +#define CR4_PGE 0x00000080 +#define CR4_PCE 0x00000100 +#define CR4_FXSR 0x00000200 +#define CR4_XMMEXCPT 0x00000400 +#define CR4_RESERVED1 0x00001800 +#define CR4_VMXE 0x00002000 +#define CR4_SMXE 0x00004000 +#define CR4_RESERVED2 0x00018000 +#define CR4_XSAVE 0x00020000 +#define CR4_RESERVED3 0xFFFC0000 + +/* Initial MXCSR control */ +#define INITIAL_MXCSR 0x1F80 + +/* Segment defintions */ +#define SEGMENT_CS 0x2E +#define SEGMENT_DS 0x3E +#define SEGMENT_ES 0x26 +#define SEGMENT_SS 0x36 +#define SEGMENT_FS 0x64 +#define SEGMENT_GS 0x65 + +/* CPUID features enumeration list */ +typedef enum _CPUID_FEATURES +{ + CPUID_FEATURES_ECX_SSE3 = 1 << 0, + CPUID_FEATURES_ECX_PCLMUL = 1 << 1, + CPUID_FEATURES_ECX_DTES64 = 1 << 2, + CPUID_FEATURES_ECX_MONITOR = 1 << 3, + CPUID_FEATURES_ECX_DS_CPL = 1 << 4, + CPUID_FEATURES_ECX_VMX = 1 << 5, + CPUID_FEATURES_ECX_SMX = 1 << 6, + CPUID_FEATURES_ECX_EST = 1 << 7, + CPUID_FEATURES_ECX_TM2 = 1 << 8, + CPUID_FEATURES_ECX_SSSE3 = 1 << 9, + CPUID_FEATURES_ECX_CID = 1 << 10, + CPUID_FEATURES_ECX_SDBG = 1 << 11, + CPUID_FEATURES_ECX_FMA = 1 << 12, + CPUID_FEATURES_ECX_CX16 = 1 << 13, + CPUID_FEATURES_ECX_XTPR = 1 << 14, + CPUID_FEATURES_ECX_PDCM = 1 << 15, + CPUID_FEATURES_ECX_PCID = 1 << 17, + CPUID_FEATURES_ECX_DCA = 1 << 18, + CPUID_FEATURES_ECX_SSE4_1 = 1 << 19, + CPUID_FEATURES_ECX_SSE4_2 = 1 << 20, + CPUID_FEATURES_ECX_X2APIC = 1 << 21, + CPUID_FEATURES_ECX_MOVBE = 1 << 22, + CPUID_FEATURES_ECX_POPCNT = 1 << 23, + CPUID_FEATURES_ECX_TSC = 1 << 24, + CPUID_FEATURES_ECX_AES = 1 << 25, + CPUID_FEATURES_ECX_XSAVE = 1 << 26, + CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, + CPUID_FEATURES_ECX_AVX = 1 << 28, + CPUID_FEATURES_ECX_F16C = 1 << 29, + CPUID_FEATURES_ECX_RDRAND = 1 << 30, + CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31, + CPUID_FEATURES_EDX_FPU = 1 << 0, + CPUID_FEATURES_EDX_VME = 1 << 1, + CPUID_FEATURES_EDX_DE = 1 << 2, + CPUID_FEATURES_EDX_PSE = 1 << 3, + CPUID_FEATURES_EDX_TSC = 1 << 4, + CPUID_FEATURES_EDX_MSR = 1 << 5, + CPUID_FEATURES_EDX_PAE = 1 << 6, + CPUID_FEATURES_EDX_MCE = 1 << 7, + CPUID_FEATURES_EDX_CX8 = 1 << 8, + CPUID_FEATURES_EDX_APIC = 1 << 9, + CPUID_FEATURES_EDX_SEP = 1 << 11, + CPUID_FEATURES_EDX_MTRR = 1 << 12, + CPUID_FEATURES_EDX_PGE = 1 << 13, + CPUID_FEATURES_EDX_MCA = 1 << 14, + CPUID_FEATURES_EDX_CMOV = 1 << 15, + CPUID_FEATURES_EDX_PAT = 1 << 16, + CPUID_FEATURES_EDX_PSE36 = 1 << 17, + CPUID_FEATURES_EDX_PSN = 1 << 18, + CPUID_FEATURES_EDX_CLFLUSH = 1 << 19, + CPUID_FEATURES_EDX_DS = 1 << 21, + CPUID_FEATURES_EDX_ACPI = 1 << 22, + CPUID_FEATURES_EDX_MMX = 1 << 23, + CPUID_FEATURES_EDX_FXSR = 1 << 24, + CPUID_FEATURES_EDX_SSE = 1 << 25, + CPUID_FEATURES_EDX_SSE2 = 1 << 26, + CPUID_FEATURES_EDX_SS = 1 << 27, + CPUID_FEATURES_EDX_HTT = 1 << 28, + CPUID_FEATURES_EDX_TM = 1 << 29, + CPUID_FEATURES_EDX_IA64 = 1 << 30, + CPUID_FEATURES_EDX_PBE = 1 << 31 +} CPUID_FEATURES, *PCPUID_FEATURES; + +/* CPUID requests */ +typedef enum _CPUID_REQUESTS +{ + CPUID_GET_VENDOR_STRING, + CPUID_GET_CPU_FEATURES, + CPUID_GET_TLB, + CPUID_GET_SERIAL +} CPUID_REQUESTS, *PCPUID_REQUESTS; + +/* CPUID registers */ +typedef struct _CPUID_REGISTERS +{ + UINT32 Leaf; + UINT32 SubLeaf; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; +} CPUID_REGISTERS, *PCPUID_REGISTERS; + +#endif /* __XTDK_I686_ARTYPES_H */ diff --git a/sdk/xtdk/i686/hlfuncs.h b/sdk/xtdk/i686/hlfuncs.h index a77ce77..cd55a7b 100644 --- a/sdk/xtdk/i686/hlfuncs.h +++ b/sdk/xtdk/i686/hlfuncs.h @@ -16,22 +16,6 @@ /* HAL library routines forward references */ -XTCDECL -VOID -HlClearInterruptFlag(); - -XTCDECL -BOOLEAN -HlCpuId(IN OUT PCPUID_REGISTERS Registers); - -XTCDECL -VOID -HlHalt(); - -XTCDECL -VOID -HlInvalidateTlbEntry(IN PVOID Address); - XTCDECL UCHAR HlIoPortInByte(IN USHORT Port); @@ -59,64 +43,4 @@ VOID HlIoPortOutLong(IN USHORT Port, IN ULONG Value); -XTCDECL -VOID -HlLoadGlobalDescriptorTable(IN PVOID Source); - -XTCDECL -VOID -HlLoadInterruptDescriptorTable(IN PVOID Source); - -XTCDECL -VOID -HlLoadSegment(IN USHORT Segment, - IN ULONG Source); - -XTCDECL -VOID -HlLoadTaskRegister(USHORT Source); - -XTCDECL -ULONG_PTR -HlReadControlRegister(IN USHORT ControlRegister); - -XTCDECL -ULONGLONG -HlReadModelSpecificRegister(IN ULONG Register); - -XTCDECL -ULONGLONG -HlReadTimeStampCounter(); - -XTCDECL -VOID -HlSetInterruptFlag(); - -XTCDECL -VOID -HlStoreGlobalDescriptorTable(OUT PVOID Destination); - -XTCDECL -VOID -HlStoreInterruptDescriptorTable(OUT PVOID Destination); - -XTCDECL -VOID -HlStoreSegment(IN USHORT Segment, - OUT PVOID Destination); - -XTCDECL -VOID -HlStoreTaskRegister(OUT PVOID Destination); - -XTCDECL -VOID -HlWriteControlRegister(IN USHORT ControlRegister, - IN UINT_PTR Value); - -XTCDECL -VOID -HlWriteModelSpecificRegister(IN ULONG Register, - IN ULONGLONG Value); - #endif /* __XTDK_I686_HLFUNCS_H */ diff --git a/sdk/xtdk/i686/hltypes.h b/sdk/xtdk/i686/hltypes.h index f5ee565..f368b1c 100644 --- a/sdk/xtdk/i686/hltypes.h +++ b/sdk/xtdk/i686/hltypes.h @@ -17,130 +17,4 @@ /* Serial port I/O addresses */ #define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8} -/* Control Register 0 constants */ -#define CR0_PE 0x00000001 -#define CR0_MP 0x00000002 -#define CR0_EM 0x00000004 -#define CR0_TS 0x00000008 -#define CR0_ET 0x00000010 -#define CR0_NE 0x00000020 -#define CR0_WP 0x00010000 -#define CR0_AM 0x00040000 -#define CR0_NW 0x20000000 -#define CR0_CD 0x40000000 -#define CR0_PG 0x80000000 - -/* Control Register 4 constants */ -#define CR4_VME 0x00000001 -#define CR4_PVI 0x00000002 -#define CR4_TSD 0x00000004 -#define CR4_DE 0x00000008 -#define CR4_PSE 0x00000010 -#define CR4_PAE 0x00000020 -#define CR4_MCE 0x00000040 -#define CR4_PGE 0x00000080 -#define CR4_PCE 0x00000100 -#define CR4_FXSR 0x00000200 -#define CR4_XMMEXCPT 0x00000400 -#define CR4_RESERVED1 0x00001800 -#define CR4_VMXE 0x00002000 -#define CR4_SMXE 0x00004000 -#define CR4_RESERVED2 0x00018000 -#define CR4_XSAVE 0x00020000 -#define CR4_RESERVED3 0xFFFC0000 - -/* Segment defintions */ -#define SEGMENT_CS 0x2E -#define SEGMENT_DS 0x3E -#define SEGMENT_ES 0x26 -#define SEGMENT_SS 0x36 -#define SEGMENT_FS 0x64 -#define SEGMENT_GS 0x65 - -/* CPUID features enumeration list */ -typedef enum _CPUID_FEATURES -{ - CPUID_FEATURES_ECX_SSE3 = 1 << 0, - CPUID_FEATURES_ECX_PCLMUL = 1 << 1, - CPUID_FEATURES_ECX_DTES64 = 1 << 2, - CPUID_FEATURES_ECX_MONITOR = 1 << 3, - CPUID_FEATURES_ECX_DS_CPL = 1 << 4, - CPUID_FEATURES_ECX_VMX = 1 << 5, - CPUID_FEATURES_ECX_SMX = 1 << 6, - CPUID_FEATURES_ECX_EST = 1 << 7, - CPUID_FEATURES_ECX_TM2 = 1 << 8, - CPUID_FEATURES_ECX_SSSE3 = 1 << 9, - CPUID_FEATURES_ECX_CID = 1 << 10, - CPUID_FEATURES_ECX_SDBG = 1 << 11, - CPUID_FEATURES_ECX_FMA = 1 << 12, - CPUID_FEATURES_ECX_CX16 = 1 << 13, - CPUID_FEATURES_ECX_XTPR = 1 << 14, - CPUID_FEATURES_ECX_PDCM = 1 << 15, - CPUID_FEATURES_ECX_PCID = 1 << 17, - CPUID_FEATURES_ECX_DCA = 1 << 18, - CPUID_FEATURES_ECX_SSE4_1 = 1 << 19, - CPUID_FEATURES_ECX_SSE4_2 = 1 << 20, - CPUID_FEATURES_ECX_X2APIC = 1 << 21, - CPUID_FEATURES_ECX_MOVBE = 1 << 22, - CPUID_FEATURES_ECX_POPCNT = 1 << 23, - CPUID_FEATURES_ECX_TSC = 1 << 24, - CPUID_FEATURES_ECX_AES = 1 << 25, - CPUID_FEATURES_ECX_XSAVE = 1 << 26, - CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, - CPUID_FEATURES_ECX_AVX = 1 << 28, - CPUID_FEATURES_ECX_F16C = 1 << 29, - CPUID_FEATURES_ECX_RDRAND = 1 << 30, - CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31, - CPUID_FEATURES_EDX_FPU = 1 << 0, - CPUID_FEATURES_EDX_VME = 1 << 1, - CPUID_FEATURES_EDX_DE = 1 << 2, - CPUID_FEATURES_EDX_PSE = 1 << 3, - CPUID_FEATURES_EDX_TSC = 1 << 4, - CPUID_FEATURES_EDX_MSR = 1 << 5, - CPUID_FEATURES_EDX_PAE = 1 << 6, - CPUID_FEATURES_EDX_MCE = 1 << 7, - CPUID_FEATURES_EDX_CX8 = 1 << 8, - CPUID_FEATURES_EDX_APIC = 1 << 9, - CPUID_FEATURES_EDX_SEP = 1 << 11, - CPUID_FEATURES_EDX_MTRR = 1 << 12, - CPUID_FEATURES_EDX_PGE = 1 << 13, - CPUID_FEATURES_EDX_MCA = 1 << 14, - CPUID_FEATURES_EDX_CMOV = 1 << 15, - CPUID_FEATURES_EDX_PAT = 1 << 16, - CPUID_FEATURES_EDX_PSE36 = 1 << 17, - CPUID_FEATURES_EDX_PSN = 1 << 18, - CPUID_FEATURES_EDX_CLFLUSH = 1 << 19, - CPUID_FEATURES_EDX_DS = 1 << 21, - CPUID_FEATURES_EDX_ACPI = 1 << 22, - CPUID_FEATURES_EDX_MMX = 1 << 23, - CPUID_FEATURES_EDX_FXSR = 1 << 24, - CPUID_FEATURES_EDX_SSE = 1 << 25, - CPUID_FEATURES_EDX_SSE2 = 1 << 26, - CPUID_FEATURES_EDX_SS = 1 << 27, - CPUID_FEATURES_EDX_HTT = 1 << 28, - CPUID_FEATURES_EDX_TM = 1 << 29, - CPUID_FEATURES_EDX_IA64 = 1 << 30, - CPUID_FEATURES_EDX_PBE = 1 << 31 -} CPUID_FEATURES, *PCPUID_FEATURES; - -/* CPUID requests */ -typedef enum _CPUID_REQUESTS -{ - CPUID_GET_VENDOR_STRING, - CPUID_GET_CPU_FEATURES, - CPUID_GET_TLB, - CPUID_GET_SERIAL -} CPUID_REQUESTS, *PCPUID_REQUESTS; - -/* CPUID registers */ -typedef struct _CPUID_REGISTERS -{ - UINT32 Leaf; - UINT32 SubLeaf; - UINT32 Eax; - UINT32 Ebx; - UINT32 Ecx; - UINT32 Edx; -} CPUID_REGISTERS, *PCPUID_REGISTERS; - #endif /* __XTDK_I686_HLTYPES_H */ diff --git a/sdk/xtdk/xtkmapi.h b/sdk/xtdk/xtkmapi.h index 312c89a..b7bc1f5 100644 --- a/sdk/xtdk/xtkmapi.h +++ b/sdk/xtdk/xtkmapi.h @@ -33,6 +33,7 @@ #include /* Architecture-specific low level data types headers */ +#include ARCH_HEADER(artypes.h) #include ARCH_HEADER(hltypes.h) #include ARCH_HEADER(ketypes.h) #include ARCH_HEADER(mmtypes.h) @@ -43,6 +44,7 @@ #include /* Architecture specific XT routines*/ +#include ARCH_HEADER(arfuncs.h) #include ARCH_HEADER(hlfuncs.h) /* Callbacks */ diff --git a/xtldr/amd64/memory.c b/xtldr/amd64/memory.c index 315fccb..b77a0c9 100644 --- a/xtldr/amd64/memory.c +++ b/xtldr/amd64/memory.c @@ -121,7 +121,7 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings, } /* Write PML4 to CR3 */ - HlWriteControlRegister(3, (UINT_PTR)*PtePointer); + ArWriteControlRegister(3, (UINT_PTR)*PtePointer); /* Return success */ return STATUS_EFI_SUCCESS; diff --git a/xtldr/i686/memory.c b/xtldr/i686/memory.c index aa62e90..39c16e1 100644 --- a/xtldr/i686/memory.c +++ b/xtldr/i686/memory.c @@ -54,7 +54,7 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings, CpuRegisters->Edx = 0; /* Get CPUID */ - HlCpuId(CpuRegisters); + ArCpuId(CpuRegisters); /* Store PAE status from the CPUID results */ if(!(CpuRegisters->Edx & CPUID_FEATURES_EDX_PAE)) @@ -215,13 +215,13 @@ BlEnablePaging(IN PLIST_ENTRY MemoryMappings, } /* Enable Physical Address Extension (PAE) */ - HlWriteControlRegister(4, HlReadControlRegister(4) | CR4_PAE); + ArWriteControlRegister(4, ArReadControlRegister(4) | CR4_PAE); /* Write page mappings to CR3 */ - HlWriteControlRegister(3, (UINT_PTR)*PtePointer); + ArWriteControlRegister(3, (UINT_PTR)*PtePointer); /* Enable paging */ - HlWriteControlRegister(0, HlReadControlRegister(0) | CR0_PG); + ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_PG); /* Return success */ return STATUS_EFI_SUCCESS; diff --git a/xtldr/modules/xtos/amd64/cpu.c b/xtldr/modules/xtos/amd64/cpu.c index 04779fc..e9f6200 100644 --- a/xtldr/modules/xtos/amd64/cpu.c +++ b/xtldr/modules/xtos/amd64/cpu.c @@ -197,7 +197,7 @@ XtpInitializeDescriptors(IN PLIST_ENTRY MemoryMappings, RtlZeroMemory(IdtEntry, EFI_SIZE_TO_PAGES(256 * sizeof(KIDTENTRY)) * EFI_PAGE_SIZE); /* Stores IDT register into new IDT entry */ - HlStoreInterruptDescriptorTable(&OriginalIdt.Limit); + ArStoreInterruptDescriptorTable(&OriginalIdt.Limit); RtlCopyMemory(IdtEntry, OriginalIdt.Base, OriginalIdt.Limit + 1); /* Map IDT and set its virtual address */ @@ -239,9 +239,9 @@ XtpLoadProcessorContext(IN PKGDTENTRY Gdt, IdtDescriptor.Limit = 256 * sizeof(KIDTENTRY) - 1; /* Load GDT, IDT and TSS */ - HlLoadGlobalDescriptorTable(&GdtDescriptor.Limit); - HlLoadInterruptDescriptorTable(&IdtDescriptor.Limit); - HlLoadTaskRegister((UINT32)KGDT_SYS_TSS); + ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit); + ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit); + ArLoadTaskRegister((UINT32)KGDT_SYS_TSS); /* Re-enable IDE interrupts */ HlIoPortOutByte(0x376, 0); @@ -280,7 +280,7 @@ XtpSetProcessorContext(IN PLIST_ENTRY MemoryMappings, XtLdrProtocol->DbgPrint(L"Setting processor context\n"); /* Disable interrupts */ - HlClearInterruptFlag(); + ArClearInterruptFlag(); /* Initialize GDT */ Status = XtpInitializeDescriptors(MemoryMappings, VirtualAddress, Gdt, Idt); diff --git a/xtldr/modules/xtos/i686/cpu.c b/xtldr/modules/xtos/i686/cpu.c index 5adfce1..eb96b7a 100644 --- a/xtldr/modules/xtos/i686/cpu.c +++ b/xtldr/modules/xtos/i686/cpu.c @@ -221,7 +221,7 @@ XtpInitializeDescriptors(IN PLIST_ENTRY MemoryMappings, RtlZeroMemory(IdtEntry, EFI_SIZE_TO_PAGES(256 * sizeof(KIDTENTRY)) * EFI_PAGE_SIZE); /* Stores IDT register into new IDT entry */ - HlStoreInterruptDescriptorTable(&OriginalIdt.Limit); + ArStoreInterruptDescriptorTable(&OriginalIdt.Limit); RtlCopyMemory(IdtEntry, OriginalIdt.Base, OriginalIdt.Limit + 1); /* Map IDT and set its virtual address */ @@ -262,12 +262,12 @@ XtpLoadProcessorContext(IN PKGDTENTRY Gdt, IdtDescriptor.Limit = 256 * sizeof(KIDTENTRY) - 1; /* Load GDT and TSS */ - HlLoadGlobalDescriptorTable(&GdtDescriptor.Limit); - HlLoadInterruptDescriptorTable(&IdtDescriptor.Limit); - HlLoadTaskRegister((UINT32)KGDT_SYS_TSS); + ArLoadGlobalDescriptorTable(&GdtDescriptor.Limit); + ArLoadInterruptDescriptorTable(&IdtDescriptor.Limit); + ArLoadTaskRegister((UINT32)KGDT_SYS_TSS); /* Load PCR in FS segment */ - HlLoadSegment(SEGMENT_FS, KGDT_R0_PCR); + ArLoadSegment(SEGMENT_FS, KGDT_R0_PCR); /* Re-enable IDE interrupts */ HlIoPortOutByte(0x376, 0); @@ -306,7 +306,7 @@ XtpSetProcessorContext(IN PLIST_ENTRY MemoryMappings, XtLdrProtocol->DbgPrint(L"Setting processor context\n"); /* Disable interrupts */ - HlClearInterruptFlag(); + ArClearInterruptFlag(); /* Initialize GDT */ Status = XtpInitializeDescriptors(MemoryMappings, VirtualAddress, Gdt, Idt); diff --git a/xtldr/xtldr.c b/xtldr/xtldr.c index 91a1912..2ef07d6 100644 --- a/xtldr/xtldr.c +++ b/xtldr/xtldr.c @@ -404,8 +404,8 @@ BlStartXtLoader(IN EFI_HANDLE ImageHandle, BlEfiPrint(L"System halted!"); for(;;) { - HlClearInterruptFlag(); - HlHalt(); + ArClearInterruptFlag(); + ArHalt(); } /* Return success */ diff --git a/xtoskrnl/CMakeLists.txt b/xtoskrnl/CMakeLists.txt index 9d85d3d..1896a8d 100644 --- a/xtoskrnl/CMakeLists.txt +++ b/xtoskrnl/CMakeLists.txt @@ -8,9 +8,10 @@ include_directories( # Specify list of source code files list(APPEND XTOSKRNL_SOURCE + ${XTOSKRNL_SOURCE_DIR}/ar/${ARCH}/cpufunc.c ${XTOSKRNL_SOURCE_DIR}/hl/cport.c ${XTOSKRNL_SOURCE_DIR}/hl/efifb.c - ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/cpufunc.c + ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/ioport.c ${XTOSKRNL_SOURCE_DIR}/ke/globals.c ${XTOSKRNL_SOURCE_DIR}/ke/krnlinit.c ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/krnlinit.c diff --git a/xtoskrnl/hl/amd64/cpufunc.c b/xtoskrnl/ar/amd64/cpufunc.c similarity index 78% rename from xtoskrnl/hl/amd64/cpufunc.c rename to xtoskrnl/ar/amd64/cpufunc.c index f2c18a5..435d8e8 100644 --- a/xtoskrnl/hl/amd64/cpufunc.c +++ b/xtoskrnl/ar/amd64/cpufunc.c @@ -1,7 +1,7 @@ /** * PROJECT: ExectOS * COPYRIGHT: See COPYING.md in the top level directory - * FILE: xtoskrnl/hl/amd64/cpufunc.c + * FILE: xtoskrnl/ar/amd64/cpufunc.c * DESCRIPTION: Routines to provide access to special AMD64 CPU instructions * DEVELOPERS: Rafal Kupiec */ @@ -18,7 +18,7 @@ */ XTCDECL VOID -HlClearInterruptFlag() +ArClearInterruptFlag() { asm volatile("cli"); } @@ -35,7 +35,7 @@ HlClearInterruptFlag() */ XTCDECL BOOLEAN -HlCpuId(IN OUT PCPUID_REGISTERS Registers) +ArCpuId(IN OUT PCPUID_REGISTERS Registers) { UINT32 MaxLeaf; @@ -76,7 +76,7 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers) */ XTCDECL VOID -HlHalt() +ArHalt() { asm volatile("hlt"); } @@ -93,7 +93,7 @@ HlHalt() */ XTCDECL VOID -HlInvalidateTlbEntry(IN PVOID Address) +ArInvalidateTlbEntry(IN PVOID Address) { asm volatile("invlpg (%0)" : @@ -101,141 +101,6 @@ HlInvalidateTlbEntry(IN PVOID Address) : "memory"); } -/** - * Reads the 8-bit data from the specified I/O port. - * - * @param Port - * Specifies the address to read from, in the range of 0-0xFFFF. - * - * @return The value read from the port. - * - * @since XT 1.0 - */ -XTCDECL -UCHAR -HlIoPortInByte(IN USHORT Port) -{ - UCHAR Value; - asm volatile("inb %1, %0" - : "=a" (Value) - : "Nd" (Port)); - return Value; -} - -/** - * Reads the 16-bit data from the specified I/O port. - * - * @param Port - * Specifies the address to read from, in the range of 0-0xFFFF. - * - * @return The value read from the port. - * - * @since XT 1.0 - */ -XTCDECL -USHORT -HlIoPortInShort(IN USHORT Port) -{ - USHORT Value; - asm volatile("inw %1, %0" - : "=a" (Value) - : "Nd" (Port)); - return Value; -} - -/** - * Reads the 32-bit data from the specified I/O port. - * - * @param Port - * Specifies the address to read from, in the range of 0-0xFFFF. - * - * @return The value read from the port. - * - * @since XT 1.0 - */ -XTCDECL -ULONG -HlIoPortInLong(IN USHORT Port) -{ - ULONG Value; - asm volatile("inl %1, %0" - : "=a" (Value) - : "Nd" (Port)); - return Value; -} - -/** - * Writes the 8-bit data to the specified I/O port. - * - * @param Port - * Specifies the address to write to, in the range of 0-0xFFFF. - * - * @param Value - * Supplies the value to write. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTCDECL -VOID -HlIoPortOutByte(IN USHORT Port, - IN UCHAR Value) -{ - asm volatile("outb %0, %1" - : - : "a" (Value), - "Nd" (Port)); -} - -/** - * Writes the 16-bit data to the specified I/O port. - * - * @param Port - * Specifies the address to write to, in the range of 0-0xFFFF. - * - * @param Value - * Supplies the value to write. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTCDECL -VOID -HlIoPortOutShort(IN USHORT Port, - IN USHORT Value) -{ - asm volatile("outw %0, %1" - : - : "a" (Value), - "Nd" (Port)); -} - -/** - * Writes the 32-bit data to the specified I/O port. - * - * @param Port - * Specifies the address to write to, in the range of 0-0xFFFF. - * - * @param Value - * Supplies the value to write. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTCDECL -VOID -HlIoPortOutLong(IN USHORT Port, - IN ULONG Value) -{ - asm volatile("outl %0, %1" - : - : "a" (Value), - "Nd" (Port)); -} - /** * Loads the values in the source operand into the global descriptor table register (GDTR). * @@ -248,7 +113,7 @@ HlIoPortOutLong(IN USHORT Port, */ XTCDECL VOID -HlLoadGlobalDescriptorTable(IN PVOID Source) +ArLoadGlobalDescriptorTable(IN PVOID Source) { asm volatile("lgdt %0" : @@ -268,7 +133,7 @@ HlLoadGlobalDescriptorTable(IN PVOID Source) */ XTCDECL VOID -HlLoadInterruptDescriptorTable(IN PVOID Source) +ArLoadInterruptDescriptorTable(IN PVOID Source) { asm volatile("lidt %0" : @@ -291,7 +156,7 @@ HlLoadInterruptDescriptorTable(IN PVOID Source) */ XTCDECL VOID -HlLoadSegment(IN USHORT Segment, +ArLoadSegment(IN USHORT Segment, IN ULONG Source) { switch(Segment) @@ -341,7 +206,7 @@ HlLoadSegment(IN USHORT Segment, */ XTCDECL VOID -HlLoadTaskRegister(USHORT Source) +ArLoadTaskRegister(USHORT Source) { asm volatile("ltr %0" : @@ -360,7 +225,7 @@ HlLoadTaskRegister(USHORT Source) */ XTCDECL ULONG_PTR -HlReadControlRegister(IN USHORT ControlRegister) +ArReadControlRegister(IN USHORT ControlRegister) { ULONG_PTR Value; @@ -423,7 +288,7 @@ HlReadControlRegister(IN USHORT ControlRegister) */ XTCDECL ULONGLONG -HlReadGSQuadWord(ULONG Offset) +ArReadGSQuadWord(ULONG Offset) { ULONGLONG Value; @@ -446,7 +311,7 @@ HlReadGSQuadWord(ULONG Offset) */ XTCDECL ULONGLONG -HlReadModelSpecificRegister(IN ULONG Register) +ArReadModelSpecificRegister(IN ULONG Register) { ULONG Low, High; @@ -467,7 +332,7 @@ HlReadModelSpecificRegister(IN ULONG Register) */ XTCDECL ULONGLONG -HlReadTimeStampCounter() +ArReadTimeStampCounter() { ULONGLONG Low, High; @@ -487,7 +352,7 @@ HlReadTimeStampCounter() */ XTCDECL VOID -HlSetInterruptFlag() +ArSetInterruptFlag() { asm volatile("sti"); } @@ -504,7 +369,7 @@ HlSetInterruptFlag() */ XTCDECL VOID -HlStoreGlobalDescriptorTable(OUT PVOID Destination) +ArStoreGlobalDescriptorTable(OUT PVOID Destination) { asm volatile("sgdt %0" : @@ -524,7 +389,7 @@ HlStoreGlobalDescriptorTable(OUT PVOID Destination) */ XTCDECL VOID -HlStoreInterruptDescriptorTable(OUT PVOID Destination) +ArStoreInterruptDescriptorTable(OUT PVOID Destination) { asm volatile("sidt %0" : @@ -547,7 +412,7 @@ HlStoreInterruptDescriptorTable(OUT PVOID Destination) */ XTCDECL VOID -HlStoreSegment(IN USHORT Segment, +ArStoreSegment(IN USHORT Segment, OUT PVOID Destination) { switch(Segment) @@ -594,7 +459,7 @@ HlStoreSegment(IN USHORT Segment, */ XTCDECL VOID -HlStoreTaskRegister(OUT PVOID Destination) +ArStoreTaskRegister(OUT PVOID Destination) { asm volatile("str %0" : @@ -617,7 +482,7 @@ HlStoreTaskRegister(OUT PVOID Destination) */ XTCDECL VOID -HlWriteControlRegister(IN USHORT ControlRegister, +ArWriteControlRegister(IN USHORT ControlRegister, IN UINT_PTR Value) { /* Write a value into specified control register */ @@ -676,7 +541,7 @@ HlWriteControlRegister(IN USHORT ControlRegister, */ XTCDECL VOID -HlWriteModelSpecificRegister(IN ULONG Register, +ArWriteModelSpecificRegister(IN ULONG Register, IN ULONGLONG Value) { ULONG Low = Value & 0xFFFFFFFF; diff --git a/xtoskrnl/hl/i686/cpufunc.c b/xtoskrnl/ar/i686/cpufunc.c similarity index 76% rename from xtoskrnl/hl/i686/cpufunc.c rename to xtoskrnl/ar/i686/cpufunc.c index 286af7c..c31c52b 100644 --- a/xtoskrnl/hl/i686/cpufunc.c +++ b/xtoskrnl/ar/i686/cpufunc.c @@ -1,7 +1,7 @@ /** * PROJECT: ExectOS * COPYRIGHT: See COPYING.md in the top level directory - * FILE: xtoskrnl/hl/i686/cpufunc.c + * FILE: xtoskrnl/ar/i686/cpufunc.c * DESCRIPTION: Routines to provide access to special i686 CPU instructions * DEVELOPERS: Rafal Kupiec */ @@ -18,7 +18,7 @@ */ XTCDECL VOID -HlClearInterruptFlag() +ArClearInterruptFlag() { asm volatile("cli"); } @@ -35,7 +35,7 @@ HlClearInterruptFlag() */ XTCDECL BOOLEAN -HlCpuId(IN OUT PCPUID_REGISTERS Registers) +ArCpuId(IN OUT PCPUID_REGISTERS Registers) { UINT32 MaxLeaf; @@ -76,7 +76,7 @@ HlCpuId(IN OUT PCPUID_REGISTERS Registers) */ XTCDECL VOID -HlHalt() +ArHalt() { asm volatile("hlt"); } @@ -93,7 +93,7 @@ HlHalt() */ XTCDECL VOID -HlInvalidateTlbEntry(PVOID Address) +ArInvalidateTlbEntry(PVOID Address) { asm volatile("invlpg (%0)" : @@ -101,141 +101,6 @@ HlInvalidateTlbEntry(PVOID Address) : "memory"); } -/** - * Reads the 8-bit data from the specified I/O port. - * - * @param Port - * Specifies the address to read from, in the range of 0-0xFFFF. - * - * @return The value read from the port. - * - * @since XT 1.0 - */ -XTCDECL -UCHAR -HlIoPortInByte(IN USHORT Port) -{ - UCHAR Value; - asm volatile("inb %1, %0" - : "=a" (Value) - : "Nd" (Port)); - return Value; -} - -/** - * Reads the 16-bit data from the specified I/O port. - * - * @param Port - * Specifies the address to read from, in the range of 0-0xFFFF. - * - * @return The value read from the port. - * - * @since XT 1.0 - */ -XTCDECL -USHORT -HlIoPortInShort(IN USHORT Port) -{ - USHORT Value; - asm volatile("inw %1, %0" - : "=a" (Value) - : "Nd" (Port)); - return Value; -} - -/** - * Reads the 32-bit data from the specified I/O port. - * - * @param Port - * Specifies the address to read from, in the range of 0-0xFFFF. - * - * @return The value read from the port. - * - * @since XT 1.0 - */ -XTCDECL -ULONG -HlIoPortInLong(IN USHORT Port) -{ - ULONG Value; - asm volatile("inl %1, %0" - : "=a" (Value) - : "Nd" (Port)); - return Value; -} - -/** - * Writes the 8-bit data to the specified I/O port. - * - * @param Port - * Specifies the address to write to, in the range of 0-0xFFFF. - * - * @param Value - * Supplies the value to write. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTCDECL -VOID -HlIoPortOutByte(IN USHORT Port, - IN UCHAR Value) -{ - asm volatile("outb %0, %1" - : - : "a" (Value), - "Nd" (Port)); -} - -/** - * Writes the 16-bit data to the specified I/O port. - * - * @param Port - * Specifies the address to write to, in the range of 0-0xFFFF. - * - * @param Value - * Supplies the value to write. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTCDECL -VOID -HlIoPortOutShort(IN USHORT Port, - IN USHORT Value) -{ - asm volatile("outw %0, %1" - : - : "a" (Value), - "Nd" (Port)); -} - -/** - * Writes the 32-bit data to the specified I/O port. - * - * @param Port - * Specifies the address to write to, in the range of 0-0xFFFF. - * - * @param Value - * Supplies the value to write. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTCDECL -VOID -HlIoPortOutLong(IN USHORT Port, - IN ULONG Value) -{ - asm volatile("outl %0, %1" - : - : "a" (Value), - "Nd" (Port)); -} - /** * Loads the values in the source operand into the global descriptor table register (GDTR). * @@ -248,7 +113,7 @@ HlIoPortOutLong(IN USHORT Port, */ XTCDECL VOID -HlLoadGlobalDescriptorTable(IN PVOID Source) +ArLoadGlobalDescriptorTable(IN PVOID Source) { asm volatile("lgdt %0" : @@ -268,7 +133,7 @@ HlLoadGlobalDescriptorTable(IN PVOID Source) */ XTCDECL VOID -HlLoadInterruptDescriptorTable(IN PVOID Source) +ArLoadInterruptDescriptorTable(IN PVOID Source) { asm volatile("lidt %0" : @@ -291,7 +156,7 @@ HlLoadInterruptDescriptorTable(IN PVOID Source) */ XTCDECL VOID -HlLoadSegment(IN USHORT Segment, +ArLoadSegment(IN USHORT Segment, IN ULONG Source) { switch(Segment) @@ -341,7 +206,7 @@ HlLoadSegment(IN USHORT Segment, */ XTCDECL VOID -HlLoadTaskRegister(USHORT Source) +ArLoadTaskRegister(USHORT Source) { asm volatile("ltr %0" : @@ -360,7 +225,7 @@ HlLoadTaskRegister(USHORT Source) */ XTCDECL ULONG_PTR -HlReadControlRegister(IN USHORT ControlRegister) +ArReadControlRegister(IN USHORT ControlRegister) { ULONG_PTR Value; @@ -417,7 +282,7 @@ HlReadControlRegister(IN USHORT ControlRegister) */ XTCDECL ULONGLONG -HlReadModelSpecificRegister(IN ULONG Register) +ArReadModelSpecificRegister(IN ULONG Register) { ULONGLONG Value; @@ -436,7 +301,7 @@ HlReadModelSpecificRegister(IN ULONG Register) */ XTCDECL ULONGLONG -HlReadTimeStampCounter() +ArReadTimeStampCounter() { ULONGLONG Value; @@ -455,7 +320,7 @@ HlReadTimeStampCounter() */ XTCDECL VOID -HlSetInterruptFlag() +ArSetInterruptFlag() { asm volatile("sti"); } @@ -472,7 +337,7 @@ HlSetInterruptFlag() */ XTCDECL VOID -HlStoreGlobalDescriptorTable(OUT PVOID Destination) +ArStoreGlobalDescriptorTable(OUT PVOID Destination) { asm volatile("sgdt %0" : @@ -492,7 +357,7 @@ HlStoreGlobalDescriptorTable(OUT PVOID Destination) */ XTCDECL VOID -HlStoreInterruptDescriptorTable(OUT PVOID Destination) +ArStoreInterruptDescriptorTable(OUT PVOID Destination) { asm volatile("sidt %0" : @@ -515,7 +380,7 @@ HlStoreInterruptDescriptorTable(OUT PVOID Destination) */ XTCDECL VOID -HlStoreSegment(IN USHORT Segment, +ArStoreSegment(IN USHORT Segment, OUT PVOID Destination) { switch(Segment) @@ -562,7 +427,7 @@ HlStoreSegment(IN USHORT Segment, */ XTCDECL VOID -HlStoreTaskRegister(OUT PVOID Destination) +ArStoreTaskRegister(OUT PVOID Destination) { asm volatile("str %0" : @@ -585,7 +450,7 @@ HlStoreTaskRegister(OUT PVOID Destination) */ XTCDECL VOID -HlWriteControlRegister(IN USHORT ControlRegister, +ArWriteControlRegister(IN USHORT ControlRegister, IN UINT_PTR Value) { /* Write a value into specified control register */ @@ -637,7 +502,7 @@ HlWriteControlRegister(IN USHORT ControlRegister, */ XTCDECL VOID -HlWriteModelSpecificRegister(IN ULONG Register, +ArWriteModelSpecificRegister(IN ULONG Register, IN ULONGLONG Value) { asm volatile("wrmsr" diff --git a/xtoskrnl/hl/amd64/ioport.c b/xtoskrnl/hl/amd64/ioport.c new file mode 100644 index 0000000..91d4a17 --- /dev/null +++ b/xtoskrnl/hl/amd64/ioport.c @@ -0,0 +1,145 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/hl/amd64/ioport.c + * DESCRIPTION: I/O port access routines for AMD64 platform + * DEVELOPERS: Rafal Kupiec + */ + +#include "xtkmapi.h" + + +/** + * Reads the 8-bit data from the specified I/O port. + * + * @param Port + * Specifies the address to read from, in the range of 0-0xFFFF. + * + * @return The value read from the port. + * + * @since XT 1.0 + */ +XTCDECL +UCHAR +HlIoPortInByte(IN USHORT Port) +{ + UCHAR Value; + asm volatile("inb %1, %0" + : "=a" (Value) + : "Nd" (Port)); + return Value; +} + +/** + * Reads the 16-bit data from the specified I/O port. + * + * @param Port + * Specifies the address to read from, in the range of 0-0xFFFF. + * + * @return The value read from the port. + * + * @since XT 1.0 + */ +XTCDECL +USHORT +HlIoPortInShort(IN USHORT Port) +{ + USHORT Value; + asm volatile("inw %1, %0" + : "=a" (Value) + : "Nd" (Port)); + return Value; +} + +/** + * Reads the 32-bit data from the specified I/O port. + * + * @param Port + * Specifies the address to read from, in the range of 0-0xFFFF. + * + * @return The value read from the port. + * + * @since XT 1.0 + */ +XTCDECL +ULONG +HlIoPortInLong(IN USHORT Port) +{ + ULONG Value; + asm volatile("inl %1, %0" + : "=a" (Value) + : "Nd" (Port)); + return Value; +} + +/** + * Writes the 8-bit data to the specified I/O port. + * + * @param Port + * Specifies the address to write to, in the range of 0-0xFFFF. + * + * @param Value + * Supplies the value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlIoPortOutByte(IN USHORT Port, + IN UCHAR Value) +{ + asm volatile("outb %0, %1" + : + : "a" (Value), + "Nd" (Port)); +} + +/** + * Writes the 16-bit data to the specified I/O port. + * + * @param Port + * Specifies the address to write to, in the range of 0-0xFFFF. + * + * @param Value + * Supplies the value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlIoPortOutShort(IN USHORT Port, + IN USHORT Value) +{ + asm volatile("outw %0, %1" + : + : "a" (Value), + "Nd" (Port)); +} + +/** + * Writes the 32-bit data to the specified I/O port. + * + * @param Port + * Specifies the address to write to, in the range of 0-0xFFFF. + * + * @param Value + * Supplies the value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlIoPortOutLong(IN USHORT Port, + IN ULONG Value) +{ + asm volatile("outl %0, %1" + : + : "a" (Value), + "Nd" (Port)); +} diff --git a/xtoskrnl/hl/i686/ioport.c b/xtoskrnl/hl/i686/ioport.c new file mode 100644 index 0000000..c46c068 --- /dev/null +++ b/xtoskrnl/hl/i686/ioport.c @@ -0,0 +1,145 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/hl/i686/ioport.c + * DESCRIPTION: I/O port access routines for i686 platform + * DEVELOPERS: Rafal Kupiec + */ + +#include "xtkmapi.h" + + +/** + * Reads the 8-bit data from the specified I/O port. + * + * @param Port + * Specifies the address to read from, in the range of 0-0xFFFF. + * + * @return The value read from the port. + * + * @since XT 1.0 + */ +XTCDECL +UCHAR +HlIoPortInByte(IN USHORT Port) +{ + UCHAR Value; + asm volatile("inb %1, %0" + : "=a" (Value) + : "Nd" (Port)); + return Value; +} + +/** + * Reads the 16-bit data from the specified I/O port. + * + * @param Port + * Specifies the address to read from, in the range of 0-0xFFFF. + * + * @return The value read from the port. + * + * @since XT 1.0 + */ +XTCDECL +USHORT +HlIoPortInShort(IN USHORT Port) +{ + USHORT Value; + asm volatile("inw %1, %0" + : "=a" (Value) + : "Nd" (Port)); + return Value; +} + +/** + * Reads the 32-bit data from the specified I/O port. + * + * @param Port + * Specifies the address to read from, in the range of 0-0xFFFF. + * + * @return The value read from the port. + * + * @since XT 1.0 + */ +XTCDECL +ULONG +HlIoPortInLong(IN USHORT Port) +{ + ULONG Value; + asm volatile("inl %1, %0" + : "=a" (Value) + : "Nd" (Port)); + return Value; +} + +/** + * Writes the 8-bit data to the specified I/O port. + * + * @param Port + * Specifies the address to write to, in the range of 0-0xFFFF. + * + * @param Value + * Supplies the value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlIoPortOutByte(IN USHORT Port, + IN UCHAR Value) +{ + asm volatile("outb %0, %1" + : + : "a" (Value), + "Nd" (Port)); +} + +/** + * Writes the 16-bit data to the specified I/O port. + * + * @param Port + * Specifies the address to write to, in the range of 0-0xFFFF. + * + * @param Value + * Supplies the value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlIoPortOutShort(IN USHORT Port, + IN USHORT Value) +{ + asm volatile("outw %0, %1" + : + : "a" (Value), + "Nd" (Port)); +} + +/** + * Writes the 32-bit data to the specified I/O port. + * + * @param Port + * Specifies the address to write to, in the range of 0-0xFFFF. + * + * @param Value + * Supplies the value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlIoPortOutLong(IN USHORT Port, + IN ULONG Value) +{ + asm volatile("outl %0, %1" + : + : "a" (Value), + "Nd" (Port)); +}