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Use __asm__ to comply with disabled GNU extensions
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This commit is contained in:
Aiken Harris 2025-08-15 11:07:07 +02:00 committed by CodingWorkshop Signing Team
parent 030575592c
commit 2e0a87e596
Signed by: CodingWorkshop Signing Team
GPG Key ID: 6DC88369C82795D2
8 changed files with 503 additions and 503 deletions
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434
xtoskrnl/ar/amd64/cpufunc.c
View File

@ -20,7 +20,7 @@ XTCDECL
VOID VOID
ArClearInterruptFlag(VOID) ArClearInterruptFlag(VOID)
{ {
asm volatile("cli"); __asm__ volatile("cli");
} }
/** /**
@ -40,12 +40,12 @@ ArCpuId(IN OUT PCPUID_REGISTERS Registers)
UINT32 MaxLeaf; UINT32 MaxLeaf;
/* Get highest function ID available */ /* Get highest function ID available */
asm volatile("cpuid" __asm__ volatile("cpuid"
: "=a" (MaxLeaf) : "=a" (MaxLeaf)
: "a" (Registers->Leaf & 0x80000000) : "a" (Registers->Leaf & 0x80000000)
: "rbx", : "rbx",
"rcx", "rcx",
"rdx"); "rdx");
/* Check if CPU supports this command */ /* Check if CPU supports this command */
if(Registers->Leaf > MaxLeaf) if(Registers->Leaf > MaxLeaf)
@ -55,13 +55,13 @@ ArCpuId(IN OUT PCPUID_REGISTERS Registers)
} }
/* Execute CPUID function */ /* Execute CPUID function */
asm volatile("cpuid" __asm__ volatile("cpuid"
: "=a" (Registers->Eax), : "=a" (Registers->Eax),
"=b" (Registers->Ebx), "=b" (Registers->Ebx),
"=c" (Registers->Ecx), "=c" (Registers->Ecx),
"=d" (Registers->Edx) "=d" (Registers->Edx)
: "a" (Registers->Leaf), : "a" (Registers->Leaf),
"c" (Registers->SubLeaf)); "c" (Registers->SubLeaf));
/* Return TRUE */ /* Return TRUE */
return TRUE; return TRUE;
@ -96,11 +96,11 @@ ArGetCpuFlags(VOID)
ULONG_PTR Flags; ULONG_PTR Flags;
/* Get RFLAGS register */ /* Get RFLAGS register */
asm volatile("pushf\n" __asm__ volatile("pushf\n"
"pop %0\n" "pop %0\n"
: "=rm" (Flags) : "=rm" (Flags)
: :
: "memory"); : "memory");
/* Return flags */ /* Return flags */
return Flags; return Flags;
@ -119,11 +119,11 @@ ULONG_PTR
ArGetStackPointer(VOID) ArGetStackPointer(VOID)
{ {
/* Get current stack pointer */ /* Get current stack pointer */
asm volatile("movq %%rsp, %%rax\n" __asm__ volatile("movq %%rsp, %%rax\n"
"retq\n" "retq\n"
: :
: :
:); :);
} }
/** /**
@ -137,7 +137,7 @@ XTCDECL
VOID VOID
ArHalt(VOID) ArHalt(VOID)
{ {
asm volatile("hlt"); __asm__ volatile("hlt");
} }
/** /**
@ -174,10 +174,10 @@ XTCDECL
VOID VOID
ArInvalidateTlbEntry(IN PVOID Address) ArInvalidateTlbEntry(IN PVOID Address)
{ {
asm volatile("invlpg (%0)" __asm__ volatile("invlpg (%0)"
: :
: "b" (Address) : "b" (Address)
: "memory"); : "memory");
} }
/** /**
@ -194,10 +194,10 @@ XTCDECL
VOID VOID
ArLoadGlobalDescriptorTable(IN PVOID Source) ArLoadGlobalDescriptorTable(IN PVOID Source)
{ {
asm volatile("lgdt %0" __asm__ volatile("lgdt %0"
: :
: "m" (*(PSHORT)Source) : "m" (*(PSHORT)Source)
: "memory"); : "memory");
} }
/** /**
@ -214,10 +214,10 @@ XTCDECL
VOID VOID
ArLoadInterruptDescriptorTable(IN PVOID Source) ArLoadInterruptDescriptorTable(IN PVOID Source)
{ {
asm volatile("lidt %0" __asm__ volatile("lidt %0"
: :
: "m" (*(PSHORT)Source) : "m" (*(PSHORT)Source)
: "memory"); : "memory");
} }
/** /**
@ -234,9 +234,9 @@ XTCDECL
VOID VOID
ArLoadLocalDescriptorTable(IN USHORT Source) ArLoadLocalDescriptorTable(IN USHORT Source)
{ {
asm volatile("lldtw %0" __asm__ volatile("lldtw %0"
: :
: "g" (Source)); : "g" (Source));
} }
/** /**
@ -253,9 +253,9 @@ XTCDECL
VOID VOID
ArLoadMxcsrRegister(IN ULONG Source) ArLoadMxcsrRegister(IN ULONG Source)
{ {
asm volatile("ldmxcsr %0" __asm__ volatile("ldmxcsr %0"
: :
: "m" (Source)); : "m" (Source));
} }
/** /**
@ -280,45 +280,45 @@ ArLoadSegment(IN USHORT Segment,
{ {
case SEGMENT_CS: case SEGMENT_CS:
/* Load CS Segment */ /* Load CS Segment */
asm volatile("mov %0, %%rax\n" __asm__ volatile("mov %0, %%rax\n"
"push %%rax\n" "push %%rax\n"
"lea label(%%rip), %%rax\n" "lea label(%%rip), %%rax\n"
"push %%rax\n" "push %%rax\n"
"lretq\n" "lretq\n"
"label:" "label:"
: :
: "ri" ((ULONGLONG)Source) : "ri" ((ULONGLONG)Source)
: "rax"); : "rax");
break; break;
case SEGMENT_DS: case SEGMENT_DS:
/* Load DS Segment */ /* Load DS Segment */
asm volatile("movl %0, %%ds" __asm__ volatile("movl %0, %%ds"
: :
: "r" (Source)); : "r" (Source));
break; break;
case SEGMENT_ES: case SEGMENT_ES:
/* Load ES Segment */ /* Load ES Segment */
asm volatile("movl %0, %%es" __asm__ volatile("movl %0, %%es"
: :
: "r" (Source)); : "r" (Source));
break; break;
case SEGMENT_FS: case SEGMENT_FS:
/* Load FS Segment */ /* Load FS Segment */
asm volatile("movl %0, %%fs" __asm__ volatile("movl %0, %%fs"
: :
: "r" (Source)); : "r" (Source));
break; break;
case SEGMENT_GS: case SEGMENT_GS:
/* Load GS Segment */ /* Load GS Segment */
asm volatile("movl %0, %%gs" __asm__ volatile("movl %0, %%gs"
: :
: "r" (Source)); : "r" (Source));
break; break;
/* Load SS Segment */ /* Load SS Segment */
case SEGMENT_SS: case SEGMENT_SS:
asm volatile("movl %0, %%ss" __asm__ volatile("movl %0, %%ss"
: :
: "r" (Source)); : "r" (Source));
break; break;
} }
} }
@ -337,9 +337,9 @@ XTCDECL
VOID VOID
ArLoadTaskRegister(USHORT Source) ArLoadTaskRegister(USHORT Source)
{ {
asm volatile("ltr %0" __asm__ volatile("ltr %0"
: :
: "rm" (Source)); : "rm" (Source));
} }
/** /**
@ -354,9 +354,9 @@ VOID
ArMemoryBarrier(VOID) ArMemoryBarrier(VOID)
{ {
LONG Barrier; LONG Barrier;
asm volatile("lock; orl $0, %0;" __asm__ volatile("lock; orl $0, %0;"
: :
: "m"(Barrier)); : "m"(Barrier));
} }
/** /**
@ -380,38 +380,38 @@ ArReadControlRegister(IN USHORT ControlRegister)
{ {
case 0: case 0:
/* Read value from CR0 */ /* Read value from CR0 */
asm volatile("mov %%cr0, %0" __asm__ volatile("mov %%cr0, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
case 2: case 2:
/* Read value from CR2 */ /* Read value from CR2 */
asm volatile("mov %%cr2, %0" __asm__ volatile("mov %%cr2, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
case 3: case 3:
/* Read value from CR3 */ /* Read value from CR3 */
asm volatile("mov %%cr3, %0" __asm__ volatile("mov %%cr3, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
case 4: case 4:
/* Read value from CR4 */ /* Read value from CR4 */
asm volatile("mov %%cr4, %0" __asm__ volatile("mov %%cr4, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
case 8: case 8:
/* Read value from CR8 */ /* Read value from CR8 */
asm volatile("mov %%cr8, %0" __asm__ volatile("mov %%cr8, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
default: default:
/* Invalid control register set */ /* Invalid control register set */
@ -444,43 +444,43 @@ ArReadDebugRegister(IN USHORT DebugRegister)
{ {
case 0: case 0:
/* Read value from DR0 */ /* Read value from DR0 */
asm volatile("mov %%dr0, %0" __asm__ volatile("mov %%dr0, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 1: case 1:
/* Read value from DR1 */ /* Read value from DR1 */
asm volatile("mov %%dr1, %0" __asm__ volatile("mov %%dr1, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 2: case 2:
/* Read value from DR2 */ /* Read value from DR2 */
asm volatile("mov %%dr2, %0" __asm__ volatile("mov %%dr2, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 3: case 3:
/* Read value from DR3 */ /* Read value from DR3 */
asm volatile("mov %%dr3, %0" __asm__ volatile("mov %%dr3, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 4: case 4:
/* Read value from DR4 */ /* Read value from DR4 */
asm volatile("mov %%dr4, %0" __asm__ volatile("mov %%dr4, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 5: case 5:
/* Read value from DR5 */ /* Read value from DR5 */
asm volatile("mov %%dr5, %0" __asm__ volatile("mov %%dr5, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 6: case 6:
/* Read value from DR6 */ /* Read value from DR6 */
asm volatile("mov %%dr6, %0" __asm__ volatile("mov %%dr6, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 7: case 7:
/* Read value from DR7 */ /* Read value from DR7 */
asm volatile("mov %%dr7, %0" __asm__ volatile("mov %%dr7, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
default: default:
/* Invalid debug register set */ /* Invalid debug register set */
@ -509,9 +509,9 @@ ArReadGSQuadWord(ULONG Offset)
ULONGLONG Value; ULONGLONG Value;
/* Read quadword from GS segment */ /* Read quadword from GS segment */
asm volatile("movq %%gs:%a[Offset], %q[Value]" __asm__ volatile("movq %%gs:%a[Offset], %q[Value]"
: [Value] "=r" (Value) : [Value] "=r" (Value)
: [Offset] "ir" (Offset)); : [Offset] "ir" (Offset));
return Value; return Value;
} }
@ -531,10 +531,10 @@ ArReadModelSpecificRegister(IN ULONG Register)
{ {
ULONG Low, High; ULONG Low, High;
asm volatile("rdmsr" __asm__ volatile("rdmsr"
: "=a" (Low), : "=a" (Low),
"=d" (High) "=d" (High)
: "c" (Register)); : "c" (Register));
return ((ULONGLONG)High << 32) | Low; return ((ULONGLONG)High << 32) | Low;
} }
@ -566,9 +566,9 @@ ArReadTimeStampCounter(VOID)
{ {
ULONGLONG Low, High; ULONGLONG Low, High;
asm volatile("rdtsc" __asm__ volatile("rdtsc"
: "=a" (Low), : "=a" (Low),
"=d" (High)); "=d" (High));
return ((ULONGLONG)High << 32) | Low; return ((ULONGLONG)High << 32) | Low;
} }
@ -584,10 +584,10 @@ XTCDECL
VOID VOID
ArReadWriteBarrier(VOID) ArReadWriteBarrier(VOID)
{ {
asm volatile("" __asm__ volatile(""
: :
: :
: "memory"); : "memory");
} }
/** /**
@ -601,7 +601,7 @@ XTCDECL
VOID VOID
ArSetInterruptFlag(VOID) ArSetInterruptFlag(VOID)
{ {
asm volatile("sti"); __asm__ volatile("sti");
} }
/** /**
@ -618,10 +618,10 @@ XTCDECL
VOID VOID
ArStoreGlobalDescriptorTable(OUT PVOID Destination) ArStoreGlobalDescriptorTable(OUT PVOID Destination)
{ {
asm volatile("sgdt %0" __asm__ volatile("sgdt %0"
: "=m" (*(PSHORT)Destination) : "=m" (*(PSHORT)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -638,10 +638,10 @@ XTCDECL
VOID VOID
ArStoreInterruptDescriptorTable(OUT PVOID Destination) ArStoreInterruptDescriptorTable(OUT PVOID Destination)
{ {
asm volatile("sidt %0" __asm__ volatile("sidt %0"
: "=m" (*(PSHORT)Destination) : "=m" (*(PSHORT)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -658,10 +658,10 @@ XTCDECL
VOID VOID
ArStoreLocalDescriptorTable(OUT PVOID Destination) ArStoreLocalDescriptorTable(OUT PVOID Destination)
{ {
asm volatile("sldt %0" __asm__ volatile("sldt %0"
: "=m" (*(PSHORT)Destination) : "=m" (*(PSHORT)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -685,28 +685,28 @@ ArStoreSegment(IN USHORT Segment,
switch(Segment) switch(Segment)
{ {
case SEGMENT_CS: case SEGMENT_CS:
asm volatile("movl %%cs, %0" __asm__ volatile("movl %%cs, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_DS: case SEGMENT_DS:
asm volatile("movl %%ds, %0" __asm__ volatile("movl %%ds, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_ES: case SEGMENT_ES:
asm volatile("movl %%es, %0" __asm__ volatile("movl %%es, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_FS: case SEGMENT_FS:
asm volatile("movl %%fs, %0" __asm__ volatile("movl %%fs, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_GS: case SEGMENT_GS:
asm volatile("movl %%gs, %0" __asm__ volatile("movl %%gs, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_SS: case SEGMENT_SS:
asm volatile("movl %%ss, %0" __asm__ volatile("movl %%ss, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
default: default:
Destination = NULL; Destination = NULL;
@ -728,10 +728,10 @@ XTCDECL
VOID VOID
ArStoreTaskRegister(OUT PVOID Destination) ArStoreTaskRegister(OUT PVOID Destination)
{ {
asm volatile("str %0" __asm__ volatile("str %0"
: "=m" (*(PULONG)Destination) : "=m" (*(PULONG)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -757,38 +757,38 @@ ArWriteControlRegister(IN USHORT ControlRegister,
{ {
case 0: case 0:
/* Write value to CR0 */ /* Write value to CR0 */
asm volatile("mov %0, %%cr0" __asm__ volatile("mov %0, %%cr0"
: :
: "r"(Value) : "r"(Value)
: "memory"); : "memory");
break; break;
case 2: case 2:
/* Write value to CR2 */ /* Write value to CR2 */
asm volatile("mov %0, %%cr2" __asm__ volatile("mov %0, %%cr2"
: :
: "r"(Value) : "r"(Value)
: "memory"); : "memory");
break; break;
case 3: case 3:
/* Write value to CR3 */ /* Write value to CR3 */
asm volatile("mov %0, %%cr3" __asm__ volatile("mov %0, %%cr3"
: :
: "r"(Value) : "r"(Value)
: "memory"); : "memory");
break; break;
case 4: case 4:
/* Write value to CR4 */ /* Write value to CR4 */
asm volatile("mov %0, %%cr4" __asm__ volatile("mov %0, %%cr4"
: :
: "r"(Value) : "r"(Value)
: "memory"); : "memory");
break; break;
case 8: case 8:
/* Write value to CR8 */ /* Write value to CR8 */
asm volatile("mov %0, %%cr8" __asm__ volatile("mov %0, %%cr8"
: :
: "r"(Value) : "r"(Value)
: "memory"); : "memory");
break; break;
} }
} }
@ -816,52 +816,52 @@ ArWriteDebugRegister(IN USHORT DebugRegister,
{ {
case 0: case 0:
/* Write value to DR0 */ /* Write value to DR0 */
asm volatile("mov %0, %%dr0" __asm__ volatile("mov %0, %%dr0"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 1: case 1:
/* Write value to DR1 */ /* Write value to DR1 */
asm volatile("mov %0, %%dr1" __asm__ volatile("mov %0, %%dr1"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 2: case 2:
/* Write value to DR2 */ /* Write value to DR2 */
asm volatile("mov %0, %%dr2" __asm__ volatile("mov %0, %%dr2"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 3: case 3:
/* Write value to DR3 */ /* Write value to DR3 */
asm volatile("mov %0, %%dr3" __asm__ volatile("mov %0, %%dr3"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 4: case 4:
/* Write value to DR4 */ /* Write value to DR4 */
asm volatile("mov %0, %%dr4" __asm__ volatile("mov %0, %%dr4"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 5: case 5:
/* Write value to DR5 */ /* Write value to DR5 */
asm volatile("mov %0, %%dr5" __asm__ volatile("mov %0, %%dr5"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 6: case 6:
/* Write value to DR6 */ /* Write value to DR6 */
asm volatile("mov %0, %%dr6" __asm__ volatile("mov %0, %%dr6"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 7: case 7:
/* Write value to DR7 */ /* Write value to DR7 */
asm volatile("mov %0, %%dr7" __asm__ volatile("mov %0, %%dr7"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
} }
} }
@ -879,10 +879,10 @@ XTCDECL
VOID VOID
ArWriteEflagsRegister(IN UINT_PTR Value) ArWriteEflagsRegister(IN UINT_PTR Value)
{ {
asm volatile("push %0\n" __asm__ volatile("push %0\n"
"popf" "popf"
: :
: "rim" (Value)); : "rim" (Value));
} }
/** /**
@ -906,11 +906,11 @@ ArWriteModelSpecificRegister(IN ULONG Register,
ULONG Low = Value & 0xFFFFFFFF; ULONG Low = Value & 0xFFFFFFFF;
ULONG High = Value >> 32; ULONG High = Value >> 32;
asm volatile("wrmsr" __asm__ volatile("wrmsr"
: :
: "c" (Register), : "c" (Register),
"a" (Low), "a" (Low),
"d" (High)); "d" (High));
} }
/** /**
@ -924,8 +924,8 @@ XTCDECL
VOID VOID
ArYieldProcessor(VOID) ArYieldProcessor(VOID)
{ {
asm volatile("pause" __asm__ volatile("pause"
: :
: :
: "memory"); : "memory");
} }

408
xtoskrnl/ar/i686/cpufunc.c
View File

@ -20,7 +20,7 @@ XTCDECL
VOID VOID
ArClearInterruptFlag(VOID) ArClearInterruptFlag(VOID)
{ {
asm volatile("cli"); __asm__ volatile("cli");
} }
/** /**
@ -40,12 +40,12 @@ ArCpuId(IN OUT PCPUID_REGISTERS Registers)
UINT32 MaxLeaf; UINT32 MaxLeaf;
/* Get highest function ID available */ /* Get highest function ID available */
asm volatile("cpuid" __asm__ volatile("cpuid"
: "=a" (MaxLeaf) : "=a" (MaxLeaf)
: "a" (Registers->Leaf & 0x80000000) : "a" (Registers->Leaf & 0x80000000)
: "rbx", : "rbx",
"rcx", "rcx",
"rdx"); "rdx");
/* Check if CPU supports this command */ /* Check if CPU supports this command */
if(Registers->Leaf > MaxLeaf) if(Registers->Leaf > MaxLeaf)
@ -55,13 +55,13 @@ ArCpuId(IN OUT PCPUID_REGISTERS Registers)
} }
/* Execute CPUID function */ /* Execute CPUID function */
asm volatile("cpuid" __asm__ volatile("cpuid"
: "=a" (Registers->Eax), : "=a" (Registers->Eax),
"=b" (Registers->Ebx), "=b" (Registers->Ebx),
"=c" (Registers->Ecx), "=c" (Registers->Ecx),
"=d" (Registers->Edx) "=d" (Registers->Edx)
: "a" (Registers->Leaf), : "a" (Registers->Leaf),
"c" (Registers->SubLeaf)); "c" (Registers->SubLeaf));
/* Return TRUE */ /* Return TRUE */
return TRUE; return TRUE;
@ -96,11 +96,11 @@ ArGetCpuFlags(VOID)
ULONG_PTR Flags; ULONG_PTR Flags;
/* Get EFLAGS register */ /* Get EFLAGS register */
asm volatile("pushf\n" __asm__ volatile("pushf\n"
"pop %0\n" "pop %0\n"
: "=rm" (Flags) : "=rm" (Flags)
: :
: "memory"); : "memory");
/* Return flags */ /* Return flags */
return Flags; return Flags;
@ -119,11 +119,11 @@ ULONG_PTR
ArGetStackPointer(VOID) ArGetStackPointer(VOID)
{ {
/* Get current stack pointer */ /* Get current stack pointer */
asm volatile("mov %%esp, %%eax\n" __asm__ volatile("mov %%esp, %%eax\n"
"ret\n" "ret\n"
: :
: :
:); :);
} }
/** /**
@ -137,7 +137,7 @@ XTCDECL
VOID VOID
ArHalt(VOID) ArHalt(VOID)
{ {
asm volatile("hlt"); __asm__ volatile("hlt");
} }
/** /**
@ -174,10 +174,10 @@ XTCDECL
VOID VOID
ArInvalidateTlbEntry(PVOID Address) ArInvalidateTlbEntry(PVOID Address)
{ {
asm volatile("invlpg (%0)" __asm__ volatile("invlpg (%0)"
: :
: "b" (Address) : "b" (Address)
: "memory"); : "memory");
} }
/** /**
@ -194,10 +194,10 @@ XTCDECL
VOID VOID
ArLoadGlobalDescriptorTable(IN PVOID Source) ArLoadGlobalDescriptorTable(IN PVOID Source)
{ {
asm volatile("lgdt %0" __asm__ volatile("lgdt %0"
: :
: "m" (*(PSHORT)Source) : "m" (*(PSHORT)Source)
: "memory"); : "memory");
} }
/** /**
@ -214,10 +214,10 @@ XTCDECL
VOID VOID
ArLoadInterruptDescriptorTable(IN PVOID Source) ArLoadInterruptDescriptorTable(IN PVOID Source)
{ {
asm volatile("lidt %0" __asm__ volatile("lidt %0"
: :
: "m" (*(PSHORT)Source) : "m" (*(PSHORT)Source)
: "memory"); : "memory");
} }
/** /**
@ -234,9 +234,9 @@ XTCDECL
VOID VOID
ArLoadLocalDescriptorTable(IN USHORT Source) ArLoadLocalDescriptorTable(IN USHORT Source)
{ {
asm volatile("lldtw %0" __asm__ volatile("lldtw %0"
: :
: "g" (Source)); : "g" (Source));
} }
/** /**
@ -261,45 +261,45 @@ ArLoadSegment(IN USHORT Segment,
{ {
case SEGMENT_CS: case SEGMENT_CS:
/* Load CS Segment */ /* Load CS Segment */
asm volatile("mov %0, %%eax\n" __asm__ volatile("mov %0, %%eax\n"
"push %%eax\n" "push %%eax\n"
"lea label, %%eax\n" "lea label, %%eax\n"
"push %%eax\n" "push %%eax\n"
"lret\n" "lret\n"
"label:" "label:"
: :
: "ri" (Source) : "ri" (Source)
: "eax"); : "eax");
break; break;
case SEGMENT_DS: case SEGMENT_DS:
/* Load DS Segment */ /* Load DS Segment */
asm volatile("movl %0, %%ds" __asm__ volatile("movl %0, %%ds"
: :
: "r" (Source)); : "r" (Source));
break; break;
case SEGMENT_ES: case SEGMENT_ES:
/* Load ES Segment */ /* Load ES Segment */
asm volatile("movl %0, %%es" __asm__ volatile("movl %0, %%es"
: :
: "r" (Source)); : "r" (Source));
break; break;
case SEGMENT_FS: case SEGMENT_FS:
/* Load FS Segment */ /* Load FS Segment */
asm volatile("movl %0, %%fs" __asm__ volatile("movl %0, %%fs"
: :
: "r" (Source)); : "r" (Source));
break; break;
case SEGMENT_GS: case SEGMENT_GS:
/* Load GS Segment */ /* Load GS Segment */
asm volatile("movl %0, %%gs" __asm__ volatile("movl %0, %%gs"
: :
: "r" (Source)); : "r" (Source));
break; break;
case SEGMENT_SS: case SEGMENT_SS:
/* Load SS Segment */ /* Load SS Segment */
asm volatile("movl %0, %%ss" __asm__ volatile("movl %0, %%ss"
: :
: "r" (Source)); : "r" (Source));
break; break;
} }
} }
@ -318,9 +318,9 @@ XTCDECL
VOID VOID
ArLoadTaskRegister(USHORT Source) ArLoadTaskRegister(USHORT Source)
{ {
asm volatile("ltr %0" __asm__ volatile("ltr %0"
: :
: "rm" (Source)); : "rm" (Source));
} }
/** /**
@ -335,10 +335,10 @@ VOID
ArMemoryBarrier(VOID) ArMemoryBarrier(VOID)
{ {
LONG Barrier; LONG Barrier;
asm volatile("xchg %%eax, %0" __asm__ volatile("xchg %%eax, %0"
: :
: "m" (Barrier) : "m" (Barrier)
: "%eax"); : "%eax");
} }
/** /**
@ -362,31 +362,31 @@ ArReadControlRegister(IN USHORT ControlRegister)
{ {
case 0: case 0:
/* Read value from CR0 */ /* Read value from CR0 */
asm volatile("mov %%cr0, %0" __asm__ volatile("mov %%cr0, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
case 2: case 2:
/* Read value from CR2 */ /* Read value from CR2 */
asm volatile("mov %%cr2, %0" __asm__ volatile("mov %%cr2, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
case 3: case 3:
/* Read value from CR3 */ /* Read value from CR3 */
asm volatile("mov %%cr3, %0" __asm__ volatile("mov %%cr3, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
case 4: case 4:
/* Read value from CR4 */ /* Read value from CR4 */
asm volatile("mov %%cr4, %0" __asm__ volatile("mov %%cr4, %0"
: "=r" (Value) : "=r" (Value)
: :
: "memory"); : "memory");
break; break;
default: default:
/* Invalid control register set */ /* Invalid control register set */
@ -419,43 +419,43 @@ ArReadDebugRegister(IN USHORT DebugRegister)
{ {
case 0: case 0:
/* Read value from DR0 */ /* Read value from DR0 */
asm volatile("mov %%dr0, %0" __asm__ volatile("mov %%dr0, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 1: case 1:
/* Read value from DR1 */ /* Read value from DR1 */
asm volatile("mov %%dr1, %0" __asm__ volatile("mov %%dr1, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 2: case 2:
/* Read value from DR2 */ /* Read value from DR2 */
asm volatile("mov %%dr2, %0" __asm__ volatile("mov %%dr2, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 3: case 3:
/* Read value from DR3 */ /* Read value from DR3 */
asm volatile("mov %%dr3, %0" __asm__ volatile("mov %%dr3, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 4: case 4:
/* Read value from DR4 */ /* Read value from DR4 */
asm volatile("mov %%dr4, %0" __asm__ volatile("mov %%dr4, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 5: case 5:
/* Read value from DR5 */ /* Read value from DR5 */
asm volatile("mov %%dr5, %0" __asm__ volatile("mov %%dr5, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 6: case 6:
/* Read value from DR6 */ /* Read value from DR6 */
asm volatile("mov %%dr6, %0" __asm__ volatile("mov %%dr6, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
case 7: case 7:
/* Read value from DR7 */ /* Read value from DR7 */
asm volatile("mov %%dr7, %0" __asm__ volatile("mov %%dr7, %0"
: "=r" (Value)); : "=r" (Value));
break; break;
default: default:
/* Invalid debug register set */ /* Invalid debug register set */
@ -482,9 +482,9 @@ ULONG
ArReadFSDualWord(ULONG Offset) ArReadFSDualWord(ULONG Offset)
{ {
ULONG Value; ULONG Value;
asm volatile("movl %%fs:%a[Offset], %k[Value]" __asm__ volatile("movl %%fs:%a[Offset], %k[Value]"
: [Value] "=r" (Value) : [Value] "=r" (Value)
: [Offset] "ir" (Offset)); : [Offset] "ir" (Offset));
return Value; return Value;
} }
@ -504,9 +504,9 @@ ArReadModelSpecificRegister(IN ULONG Register)
{ {
ULONGLONG Value; ULONGLONG Value;
asm volatile("rdmsr" __asm__ volatile("rdmsr"
: "=A" (Value) : "=A" (Value)
: "c" (Register)); : "c" (Register));
return Value; return Value;
} }
@ -537,8 +537,8 @@ ArReadTimeStampCounter(VOID)
{ {
ULONGLONG Value; ULONGLONG Value;
asm volatile("rdtsc" __asm__ volatile("rdtsc"
: "=A" (Value)); : "=A" (Value));
return Value; return Value;
} }
@ -554,10 +554,10 @@ XTCDECL
VOID VOID
ArReadWriteBarrier(VOID) ArReadWriteBarrier(VOID)
{ {
asm volatile("" __asm__ volatile(""
: :
: :
: "memory"); : "memory");
} }
/** /**
@ -571,7 +571,7 @@ XTCDECL
VOID VOID
ArSetInterruptFlag(VOID) ArSetInterruptFlag(VOID)
{ {
asm volatile("sti"); __asm__ volatile("sti");
} }
/** /**
@ -588,10 +588,10 @@ XTCDECL
VOID VOID
ArStoreGlobalDescriptorTable(OUT PVOID Destination) ArStoreGlobalDescriptorTable(OUT PVOID Destination)
{ {
asm volatile("sgdt %0" __asm__ volatile("sgdt %0"
: "=m" (*(PSHORT)Destination) : "=m" (*(PSHORT)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -608,10 +608,10 @@ XTCDECL
VOID VOID
ArStoreInterruptDescriptorTable(OUT PVOID Destination) ArStoreInterruptDescriptorTable(OUT PVOID Destination)
{ {
asm volatile("sidt %0" __asm__ volatile("sidt %0"
: "=m" (*(PSHORT)Destination) : "=m" (*(PSHORT)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -628,10 +628,10 @@ XTCDECL
VOID VOID
ArStoreLocalDescriptorTable(OUT PVOID Destination) ArStoreLocalDescriptorTable(OUT PVOID Destination)
{ {
asm volatile("sldt %0" __asm__ volatile("sldt %0"
: "=m" (*(PSHORT)Destination) : "=m" (*(PSHORT)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -655,28 +655,28 @@ ArStoreSegment(IN USHORT Segment,
switch(Segment) switch(Segment)
{ {
case SEGMENT_CS: case SEGMENT_CS:
asm volatile("movl %%cs, %0" __asm__ volatile("movl %%cs, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_DS: case SEGMENT_DS:
asm volatile("movl %%ds, %0" __asm__ volatile("movl %%ds, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_ES: case SEGMENT_ES:
asm volatile("movl %%es, %0" __asm__ volatile("movl %%es, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_FS: case SEGMENT_FS:
asm volatile("movl %%fs, %0" __asm__ volatile("movl %%fs, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_GS: case SEGMENT_GS:
asm volatile("movl %%gs, %0" __asm__ volatile("movl %%gs, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
case SEGMENT_SS: case SEGMENT_SS:
asm volatile("movl %%ss, %0" __asm__ volatile("movl %%ss, %0"
: "=r" (*(PUINT)Destination)); : "=r" (*(PUINT)Destination));
break; break;
default: default:
Destination = NULL; Destination = NULL;
@ -698,10 +698,10 @@ XTCDECL
VOID VOID
ArStoreTaskRegister(OUT PVOID Destination) ArStoreTaskRegister(OUT PVOID Destination)
{ {
asm volatile("str %0" __asm__ volatile("str %0"
: "=m" (*(PULONG)Destination) : "=m" (*(PULONG)Destination)
: :
: "memory"); : "memory");
} }
/** /**
@ -727,31 +727,31 @@ ArWriteControlRegister(IN USHORT ControlRegister,
{ {
case 0: case 0:
/* Write value to CR0 */ /* Write value to CR0 */
asm volatile("mov %0, %%cr0" __asm__ volatile("mov %0, %%cr0"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
break; break;
case 2: case 2:
/* Write value to CR2 */ /* Write value to CR2 */
asm volatile("mov %0, %%cr2" __asm__ volatile("mov %0, %%cr2"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
break; break;
case 3: case 3:
/* Write value to CR3 */ /* Write value to CR3 */
asm volatile("mov %0, %%cr3" __asm__ volatile("mov %0, %%cr3"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
break; break;
case 4: case 4:
/* Write value to CR4 */ /* Write value to CR4 */
asm volatile("mov %0, %%cr4" __asm__ volatile("mov %0, %%cr4"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
break; break;
} }
} }
@ -779,52 +779,52 @@ ArWriteDebugRegister(IN USHORT DebugRegister,
{ {
case 0: case 0:
/* Write value to DR0 */ /* Write value to DR0 */
asm volatile("mov %0, %%dr0" __asm__ volatile("mov %0, %%dr0"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 1: case 1:
/* Write value to DR1 */ /* Write value to DR1 */
asm volatile("mov %0, %%dr1" __asm__ volatile("mov %0, %%dr1"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 2: case 2:
/* Write value to DR2 */ /* Write value to DR2 */
asm volatile("mov %0, %%dr2" __asm__ volatile("mov %0, %%dr2"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 3: case 3:
/* Write value to DR3 */ /* Write value to DR3 */
asm volatile("mov %0, %%dr3" __asm__ volatile("mov %0, %%dr3"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 4: case 4:
/* Write value to DR4 */ /* Write value to DR4 */
asm volatile("mov %0, %%dr4" __asm__ volatile("mov %0, %%dr4"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 5: case 5:
/* Write value to DR5 */ /* Write value to DR5 */
asm volatile("mov %0, %%dr5" __asm__ volatile("mov %0, %%dr5"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 6: case 6:
/* Write value to DR6 */ /* Write value to DR6 */
asm volatile("mov %0, %%dr6" __asm__ volatile("mov %0, %%dr6"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
case 7: case 7:
/* Write value to DR7 */ /* Write value to DR7 */
asm volatile("mov %0, %%dr7" __asm__ volatile("mov %0, %%dr7"
: :
: "r" (Value) : "r" (Value)
: "memory"); : "memory");
} }
} }
@ -842,10 +842,10 @@ XTCDECL
VOID VOID
ArWriteEflagsRegister(IN UINT_PTR Value) ArWriteEflagsRegister(IN UINT_PTR Value)
{ {
asm volatile("push %0\n" __asm__ volatile("push %0\n"
"popf" "popf"
: :
: "rim" (Value)); : "rim" (Value));
} }
/** /**
@ -866,10 +866,10 @@ VOID
ArWriteModelSpecificRegister(IN ULONG Register, ArWriteModelSpecificRegister(IN ULONG Register,
IN ULONGLONG Value) IN ULONGLONG Value)
{ {
asm volatile("wrmsr" __asm__ volatile("wrmsr"
: :
: "c" (Register), : "c" (Register),
"A" (Value)); "A" (Value));
} }
/** /**
@ -883,8 +883,8 @@ XTCDECL
VOID VOID
ArYieldProcessor(VOID) ArYieldProcessor(VOID)
{ {
asm volatile("pause" __asm__ volatile("pause"
: :
: :
: "memory"); : "memory");
} }

42
xtoskrnl/hl/amd64/ioport.c
View File

@ -24,9 +24,9 @@ UCHAR
HlIoPortInByte(IN USHORT Port) HlIoPortInByte(IN USHORT Port)
{ {
UCHAR Value; UCHAR Value;
asm volatile("inb %1, %0" __asm__ volatile("inb %1, %0"
: "=a" (Value) : "=a" (Value)
: "Nd" (Port)); : "Nd" (Port));
return Value; return Value;
} }
@ -45,9 +45,9 @@ ULONG
HlIoPortInLong(IN USHORT Port) HlIoPortInLong(IN USHORT Port)
{ {
ULONG Value; ULONG Value;
asm volatile("inl %1, %0" __asm__ volatile("inl %1, %0"
: "=a" (Value) : "=a" (Value)
: "Nd" (Port)); : "Nd" (Port));
return Value; return Value;
} }
@ -66,9 +66,9 @@ USHORT
HlIoPortInShort(IN USHORT Port) HlIoPortInShort(IN USHORT Port)
{ {
USHORT Value; USHORT Value;
asm volatile("inw %1, %0" __asm__ volatile("inw %1, %0"
: "=a" (Value) : "=a" (Value)
: "Nd" (Port)); : "Nd" (Port));
return Value; return Value;
} }
@ -90,10 +90,10 @@ VOID
HlIoPortOutByte(IN USHORT Port, HlIoPortOutByte(IN USHORT Port,
IN UCHAR Value) IN UCHAR Value)
{ {
asm volatile("outb %0, %1" __asm__ volatile("outb %0, %1"
: :
: "a" (Value), : "a" (Value),
"Nd" (Port)); "Nd" (Port));
} }
/** /**
@ -114,10 +114,10 @@ VOID
HlIoPortOutLong(IN USHORT Port, HlIoPortOutLong(IN USHORT Port,
IN ULONG Value) IN ULONG Value)
{ {
asm volatile("outl %0, %1" __asm__ volatile("outl %0, %1"
: :
: "a" (Value), : "a" (Value),
"Nd" (Port)); "Nd" (Port));
} }
/** /**
@ -138,8 +138,8 @@ VOID
HlIoPortOutShort(IN USHORT Port, HlIoPortOutShort(IN USHORT Port,
IN USHORT Value) IN USHORT Value)
{ {
asm volatile("outw %0, %1" __asm__ volatile("outw %0, %1"
: :
: "a" (Value), : "a" (Value),
"Nd" (Port)); "Nd" (Port));
} }

42
xtoskrnl/hl/i686/ioport.c
View File

@ -24,9 +24,9 @@ UCHAR
HlIoPortInByte(IN USHORT Port) HlIoPortInByte(IN USHORT Port)
{ {
UCHAR Value; UCHAR Value;
asm volatile("inb %1, %0" __asm__ volatile("inb %1, %0"
: "=a" (Value) : "=a" (Value)
: "Nd" (Port)); : "Nd" (Port));
return Value; return Value;
} }
@ -45,9 +45,9 @@ ULONG
HlIoPortInLong(IN USHORT Port) HlIoPortInLong(IN USHORT Port)
{ {
ULONG Value; ULONG Value;
asm volatile("inl %1, %0" __asm__ volatile("inl %1, %0"
: "=a" (Value) : "=a" (Value)
: "Nd" (Port)); : "Nd" (Port));
return Value; return Value;
} }
@ -66,9 +66,9 @@ USHORT
HlIoPortInShort(IN USHORT Port) HlIoPortInShort(IN USHORT Port)
{ {
USHORT Value; USHORT Value;
asm volatile("inw %1, %0" __asm__ volatile("inw %1, %0"
: "=a" (Value) : "=a" (Value)
: "Nd" (Port)); : "Nd" (Port));
return Value; return Value;
} }
@ -90,10 +90,10 @@ VOID
HlIoPortOutByte(IN USHORT Port, HlIoPortOutByte(IN USHORT Port,
IN UCHAR Value) IN UCHAR Value)
{ {
asm volatile("outb %0, %1" __asm__ volatile("outb %0, %1"
: :
: "a" (Value), : "a" (Value),
"Nd" (Port)); "Nd" (Port));
} }
/** /**
@ -114,10 +114,10 @@ VOID
HlIoPortOutLong(IN USHORT Port, HlIoPortOutLong(IN USHORT Port,
IN ULONG Value) IN ULONG Value)
{ {
asm volatile("outl %0, %1" __asm__ volatile("outl %0, %1"
: :
: "a" (Value), : "a" (Value),
"Nd" (Port)); "Nd" (Port));
} }
/** /**
@ -138,8 +138,8 @@ VOID
HlIoPortOutShort(IN USHORT Port, HlIoPortOutShort(IN USHORT Port,
IN USHORT Value) IN USHORT Value)
{ {
asm volatile("outw %0, %1" __asm__ volatile("outw %0, %1"
: :
: "a" (Value), : "a" (Value),
"Nd" (Port)); "Nd" (Port));
} }

18
xtoskrnl/ke/amd64/krnlinit.c
View File

@ -122,13 +122,13 @@ VOID
KepSwitchBootStack(IN ULONG_PTR Stack) KepSwitchBootStack(IN ULONG_PTR Stack)
{ {
/* Discard old stack frame, switch stack and jump to KepStartKernel() */ /* Discard old stack frame, switch stack and jump to KepStartKernel() */
asm volatile("mov %0, %%rdx\n" __asm__ volatile("mov %0, %%rdx\n"
"xor %%rbp, %%rbp\n" "xor %%rbp, %%rbp\n"
"mov %%rdx, %%rsp\n" "mov %%rdx, %%rsp\n"
"sub %1, %%rsp\n" "sub %1, %%rsp\n"
"jmp KepStartKernel\n" "jmp KepStartKernel\n"
: :
: "m" (Stack), : "m" (Stack),
"i" (FLOATING_SAVE_AREA_SIZE | KEXCEPTION_FRAME_SIZE | KSWITCH_FRAME_SIZE | KRETURN_ADDRESS_SIZE), "i" (FLOATING_SAVE_AREA_SIZE | KEXCEPTION_FRAME_SIZE | KSWITCH_FRAME_SIZE | KRETURN_ADDRESS_SIZE),
"p" (KepStartKernel)); "p" (KepStartKernel));
} }

22
xtoskrnl/ke/i686/krnlinit.c
View File

@ -122,15 +122,15 @@ VOID
KepSwitchBootStack(IN ULONG_PTR Stack) KepSwitchBootStack(IN ULONG_PTR Stack)
{ {
/* Discard old stack frame, switch stack, make space for NPX and jump to KepStartKernel() */ /* Discard old stack frame, switch stack, make space for NPX and jump to KepStartKernel() */
asm volatile("mov %0, %%edx\n" __asm__ volatile("mov %0, %%edx\n"
"xor %%ebp, %%ebp\n" "xor %%ebp, %%ebp\n"
"mov %%edx, %%esp\n" "mov %%edx, %%esp\n"
"sub %1, %%esp\n" "sub %1, %%esp\n"
"push %2\n" "push %2\n"
"jmp _KepStartKernel@0\n" "jmp _KepStartKernel@0\n"
: :
: "m" (Stack), : "m" (Stack),
"i" (KTRAP_FRAME_ALIGN | KTRAP_FRAME_SIZE | NPX_FRAME_SIZE | KRETURN_ADDRESS_SIZE), "i" (KTRAP_FRAME_ALIGN | KTRAP_FRAME_SIZE | NPX_FRAME_SIZE | KRETURN_ADDRESS_SIZE),
"i" (CR0_EM | CR0_MP | CR0_TS), "i" (CR0_EM | CR0_MP | CR0_TS),
"p" (KepStartKernel)); "p" (KepStartKernel));
} }

24
xtoskrnl/mm/amd64/pages.c
View File

@ -27,16 +27,16 @@ VOID
MmZeroPages(IN PVOID Address, MmZeroPages(IN PVOID Address,
IN ULONG Size) IN ULONG Size)
{ {
asm volatile("xor %%rax, %%rax\n" __asm__ volatile("xor %%rax, %%rax\n"
"mov %0, %%rdi\n" "mov %0, %%rdi\n"
"mov %1, %%ecx\n" "mov %1, %%ecx\n"
"shr $3, %%ecx\n" "shr $3, %%ecx\n"
"rep stosq\n" "rep stosq\n"
: :
: "m" (Address), : "m" (Address),
"m" (Size) "m" (Size)
: "rax", : "rax",
"rdi", "rdi",
"ecx", "ecx",
"memory"); "memory");
} }

16
xtoskrnl/mm/i686/pages.c
View File

@ -27,12 +27,12 @@ VOID
MmZeroPages(IN PVOID Address, MmZeroPages(IN PVOID Address,
IN ULONG Size) IN ULONG Size)
{ {
asm volatile("xor %%eax, %%eax\n" __asm__ volatile("xor %%eax, %%eax\n"
"rep stosb" "rep stosb"
: "=D"(Address), : "=D"(Address),
"=c"(Size) "=c"(Size)
: "0"(Address), : "0"(Address),
"1"(Size), "1"(Size),
"a"(0) "a"(0)
: "memory"); : "memory");
} }