diff --git a/sdk/xtdk/amd64/hlfuncs.h b/sdk/xtdk/amd64/hlfuncs.h index 0662ed5..e7594d1 100644 --- a/sdk/xtdk/amd64/hlfuncs.h +++ b/sdk/xtdk/amd64/hlfuncs.h @@ -18,6 +18,10 @@ extern ULONG ComPortAddress[]; /* HAL library routines forward references */ +XTAPI +BOOLEAN +HlCpuId(IN OUT PCPUID_REGISTERS Registers); + XTAPI UCHAR HlIoPortInByte(IN USHORT Port); diff --git a/sdk/xtdk/amd64/hltypes.h b/sdk/xtdk/amd64/hltypes.h new file mode 100644 index 0000000..ec00432 --- /dev/null +++ b/sdk/xtdk/amd64/hltypes.h @@ -0,0 +1,100 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: sdk/xtdk/amd64/hltypes.h + * DESCRIPTION: XT hardware abstraction layer structures definitions specific to AMD64 architecture + * DEVELOPERS: Rafal Kupiec + */ + +#ifndef __XTDK_AMD64_HLTYPES_H +#define __XTDK_AMD64_HLTYPES_H + +#include "xtdefs.h" +#include "xtstruct.h" +#include "xttypes.h" + + +typedef enum _CPUID_FEATURES +{ + CPUID_FEATURES_ECX_SSE3 = 1 << 0, + CPUID_FEATURES_ECX_PCLMUL = 1 << 1, + CPUID_FEATURES_ECX_DTES64 = 1 << 2, + CPUID_FEATURES_ECX_MONITOR = 1 << 3, + CPUID_FEATURES_ECX_DS_CPL = 1 << 4, + CPUID_FEATURES_ECX_VMX = 1 << 5, + CPUID_FEATURES_ECX_SMX = 1 << 6, + CPUID_FEATURES_ECX_EST = 1 << 7, + CPUID_FEATURES_ECX_TM2 = 1 << 8, + CPUID_FEATURES_ECX_SSSE3 = 1 << 9, + CPUID_FEATURES_ECX_CID = 1 << 10, + CPUID_FEATURES_ECX_SDBG = 1 << 11, + CPUID_FEATURES_ECX_FMA = 1 << 12, + CPUID_FEATURES_ECX_CX16 = 1 << 13, + CPUID_FEATURES_ECX_XTPR = 1 << 14, + CPUID_FEATURES_ECX_PDCM = 1 << 15, + CPUID_FEATURES_ECX_PCID = 1 << 17, + CPUID_FEATURES_ECX_DCA = 1 << 18, + CPUID_FEATURES_ECX_SSE4_1 = 1 << 19, + CPUID_FEATURES_ECX_SSE4_2 = 1 << 20, + CPUID_FEATURES_ECX_X2APIC = 1 << 21, + CPUID_FEATURES_ECX_MOVBE = 1 << 22, + CPUID_FEATURES_ECX_POPCNT = 1 << 23, + CPUID_FEATURES_ECX_TSC = 1 << 24, + CPUID_FEATURES_ECX_AES = 1 << 25, + CPUID_FEATURES_ECX_XSAVE = 1 << 26, + CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, + CPUID_FEATURES_ECX_AVX = 1 << 28, + CPUID_FEATURES_ECX_F16C = 1 << 29, + CPUID_FEATURES_ECX_RDRAND = 1 << 30, + CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31, + CPUID_FEATURES_EDX_FPU = 1 << 0, + CPUID_FEATURES_EDX_VME = 1 << 1, + CPUID_FEATURES_EDX_DE = 1 << 2, + CPUID_FEATURES_EDX_PSE = 1 << 3, + CPUID_FEATURES_EDX_TSC = 1 << 4, + CPUID_FEATURES_EDX_MSR = 1 << 5, + CPUID_FEATURES_EDX_PAE = 1 << 6, + CPUID_FEATURES_EDX_MCE = 1 << 7, + CPUID_FEATURES_EDX_CX8 = 1 << 8, + CPUID_FEATURES_EDX_APIC = 1 << 9, + CPUID_FEATURES_EDX_SEP = 1 << 11, + CPUID_FEATURES_EDX_MTRR = 1 << 12, + CPUID_FEATURES_EDX_PGE = 1 << 13, + CPUID_FEATURES_EDX_MCA = 1 << 14, + CPUID_FEATURES_EDX_CMOV = 1 << 15, + CPUID_FEATURES_EDX_PAT = 1 << 16, + CPUID_FEATURES_EDX_PSE36 = 1 << 17, + CPUID_FEATURES_EDX_PSN = 1 << 18, + CPUID_FEATURES_EDX_CLFLUSH = 1 << 19, + CPUID_FEATURES_EDX_DS = 1 << 21, + CPUID_FEATURES_EDX_ACPI = 1 << 22, + CPUID_FEATURES_EDX_MMX = 1 << 23, + CPUID_FEATURES_EDX_FXSR = 1 << 24, + CPUID_FEATURES_EDX_SSE = 1 << 25, + CPUID_FEATURES_EDX_SSE2 = 1 << 26, + CPUID_FEATURES_EDX_SS = 1 << 27, + CPUID_FEATURES_EDX_HTT = 1 << 28, + CPUID_FEATURES_EDX_TM = 1 << 29, + CPUID_FEATURES_EDX_IA64 = 1 << 30, + CPUID_FEATURES_EDX_PBE = 1 << 31 +} CPUID_FEATURES, *PCPUID_FEATURES; + +typedef enum _CPUID_REQUESTS +{ + CPUID_GET_VENDOR_STRING, + CPUID_GET_CPU_FEATURES, + CPUID_GET_TLB, + CPUID_GET_SERIAL +} CPUID_REQUESTS, *PCPUID_REQUESTS; + +typedef struct _CPUID_REGISTERS +{ + UINT32 Leaf; + UINT32 SubLeaf; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; +} CPUID_REGISTERS, *PCPUID_REGISTERS; + +#endif /* __XTDK_AMD64_HLTYPES_H */ diff --git a/sdk/xtdk/amd64/xtstruct.h b/sdk/xtdk/amd64/xtstruct.h index bb6087e..d976ab0 100644 --- a/sdk/xtdk/amd64/xtstruct.h +++ b/sdk/xtdk/amd64/xtstruct.h @@ -11,5 +11,7 @@ /* Architecture-related structures forward references */ +typedef struct _CPUID_REGISTERS CPUID_REGISTERS, *PCPUID_REGISTERS; +typedef struct _HARDWARE_PTE HARDWARE_PTE, *PHARDWARE_PTE; #endif /* __XTDK_AMD64_XTSTRUCT_H */ diff --git a/sdk/xtdk/i686/hlfuncs.h b/sdk/xtdk/i686/hlfuncs.h index caf000e..35597af 100644 --- a/sdk/xtdk/i686/hlfuncs.h +++ b/sdk/xtdk/i686/hlfuncs.h @@ -18,6 +18,10 @@ extern ULONG ComPortAddress[]; /* HAL library routines forward references */ +XTAPI +BOOLEAN +HlCpuId(IN OUT PCPUID_REGISTERS Registers); + XTAPI UCHAR HlIoPortInByte(IN USHORT Port); @@ -45,18 +49,18 @@ HlReadCR4(); XTAPI VOID -HlWriteCR0(UINT_PTR Data); +HlWriteCR0(IN UINT_PTR Data); XTAPI VOID -HlWriteCR2(UINT_PTR Data); +HlWriteCR2(IN UINT_PTR Data); XTAPI VOID -HlWriteCR3(UINT_PTR Data); +HlWriteCR3(IN UINT_PTR Data); XTAPI VOID -HlWriteCR4(UINT_PTR Data); +HlWriteCR4(IN UINT_PTR Data); #endif /* __XTDK_I686_HLFUNCS_H */ diff --git a/sdk/xtdk/i686/hltypes.h b/sdk/xtdk/i686/hltypes.h new file mode 100644 index 0000000..f63cb6d --- /dev/null +++ b/sdk/xtdk/i686/hltypes.h @@ -0,0 +1,100 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: sdk/xtdk/i686/hltypes.h + * DESCRIPTION: XT hardware abstraction layer structures definitions specific to i686 architecture + * DEVELOPERS: Rafal Kupiec + */ + +#ifndef __XTDK_I686_HLTYPES_H +#define __XTDK_I686_HLTYPES_H + +#include "xtdefs.h" +#include "xtstruct.h" +#include "xttypes.h" + + +typedef enum _CPUID_FEATURES +{ + CPUID_FEATURES_ECX_SSE3 = 1 << 0, + CPUID_FEATURES_ECX_PCLMUL = 1 << 1, + CPUID_FEATURES_ECX_DTES64 = 1 << 2, + CPUID_FEATURES_ECX_MONITOR = 1 << 3, + CPUID_FEATURES_ECX_DS_CPL = 1 << 4, + CPUID_FEATURES_ECX_VMX = 1 << 5, + CPUID_FEATURES_ECX_SMX = 1 << 6, + CPUID_FEATURES_ECX_EST = 1 << 7, + CPUID_FEATURES_ECX_TM2 = 1 << 8, + CPUID_FEATURES_ECX_SSSE3 = 1 << 9, + CPUID_FEATURES_ECX_CID = 1 << 10, + CPUID_FEATURES_ECX_SDBG = 1 << 11, + CPUID_FEATURES_ECX_FMA = 1 << 12, + CPUID_FEATURES_ECX_CX16 = 1 << 13, + CPUID_FEATURES_ECX_XTPR = 1 << 14, + CPUID_FEATURES_ECX_PDCM = 1 << 15, + CPUID_FEATURES_ECX_PCID = 1 << 17, + CPUID_FEATURES_ECX_DCA = 1 << 18, + CPUID_FEATURES_ECX_SSE4_1 = 1 << 19, + CPUID_FEATURES_ECX_SSE4_2 = 1 << 20, + CPUID_FEATURES_ECX_X2APIC = 1 << 21, + CPUID_FEATURES_ECX_MOVBE = 1 << 22, + CPUID_FEATURES_ECX_POPCNT = 1 << 23, + CPUID_FEATURES_ECX_TSC = 1 << 24, + CPUID_FEATURES_ECX_AES = 1 << 25, + CPUID_FEATURES_ECX_XSAVE = 1 << 26, + CPUID_FEATURES_ECX_OSXSAVE = 1 << 27, + CPUID_FEATURES_ECX_AVX = 1 << 28, + CPUID_FEATURES_ECX_F16C = 1 << 29, + CPUID_FEATURES_ECX_RDRAND = 1 << 30, + CPUID_FEATURES_ECX_HYPERVISOR = 1 << 31, + CPUID_FEATURES_EDX_FPU = 1 << 0, + CPUID_FEATURES_EDX_VME = 1 << 1, + CPUID_FEATURES_EDX_DE = 1 << 2, + CPUID_FEATURES_EDX_PSE = 1 << 3, + CPUID_FEATURES_EDX_TSC = 1 << 4, + CPUID_FEATURES_EDX_MSR = 1 << 5, + CPUID_FEATURES_EDX_PAE = 1 << 6, + CPUID_FEATURES_EDX_MCE = 1 << 7, + CPUID_FEATURES_EDX_CX8 = 1 << 8, + CPUID_FEATURES_EDX_APIC = 1 << 9, + CPUID_FEATURES_EDX_SEP = 1 << 11, + CPUID_FEATURES_EDX_MTRR = 1 << 12, + CPUID_FEATURES_EDX_PGE = 1 << 13, + CPUID_FEATURES_EDX_MCA = 1 << 14, + CPUID_FEATURES_EDX_CMOV = 1 << 15, + CPUID_FEATURES_EDX_PAT = 1 << 16, + CPUID_FEATURES_EDX_PSE36 = 1 << 17, + CPUID_FEATURES_EDX_PSN = 1 << 18, + CPUID_FEATURES_EDX_CLFLUSH = 1 << 19, + CPUID_FEATURES_EDX_DS = 1 << 21, + CPUID_FEATURES_EDX_ACPI = 1 << 22, + CPUID_FEATURES_EDX_MMX = 1 << 23, + CPUID_FEATURES_EDX_FXSR = 1 << 24, + CPUID_FEATURES_EDX_SSE = 1 << 25, + CPUID_FEATURES_EDX_SSE2 = 1 << 26, + CPUID_FEATURES_EDX_SS = 1 << 27, + CPUID_FEATURES_EDX_HTT = 1 << 28, + CPUID_FEATURES_EDX_TM = 1 << 29, + CPUID_FEATURES_EDX_IA64 = 1 << 30, + CPUID_FEATURES_EDX_PBE = 1 << 31 +} CPUID_FEATURES, *PCPUID_FEATURES; + +typedef enum _CPUID_REQUESTS +{ + CPUID_GET_VENDOR_STRING, + CPUID_GET_CPU_FEATURES, + CPUID_GET_TLB, + CPUID_GET_SERIAL +} CPUID_REQUESTS, *PCPUID_REQUESTS; + +typedef struct _CPUID_REGISTERS +{ + UINT32 Leaf; + UINT32 SubLeaf; + UINT32 Eax; + UINT32 Ebx; + UINT32 Ecx; + UINT32 Edx; +} CPUID_REGISTERS, *PCPUID_REGISTERS; + +#endif /* __XTDK_I686_HLTYPES_H */ diff --git a/sdk/xtdk/i686/xtstruct.h b/sdk/xtdk/i686/xtstruct.h index 0e6b775..e01d4cf 100644 --- a/sdk/xtdk/i686/xtstruct.h +++ b/sdk/xtdk/i686/xtstruct.h @@ -11,5 +11,8 @@ /* Architecture-related structures forward references */ +typedef struct _CPUID_REGISTERS CPUID_REGISTERS, *PCPUID_REGISTERS; +typedef struct _HARDWARE_PTE HARDWARE_PTE, *PHARDWARE_PTE; +typedef struct _HARDWARE_PTE_PAE HARDWARE_PTE_PAE, *PHARDWARE_PTE_PAE; #endif /* __XTDK_I686_XTSTRUCT_H */ diff --git a/sdk/xtdk/xtkmapi.h b/sdk/xtdk/xtkmapi.h index f3c52b8..741692f 100644 --- a/sdk/xtdk/xtkmapi.h +++ b/sdk/xtdk/xtkmapi.h @@ -30,6 +30,7 @@ #include "hltypes.h" /* Architecture-specific low level data types headers */ +#include ARCH_HEADER(hltypes.h) #include ARCH_HEADER(mmtypes.h) /* XT routines */ diff --git a/xtoskrnl/hl/amd64/cpufunc.c b/xtoskrnl/hl/amd64/cpufunc.c index 608f005..267d0d1 100644 --- a/xtoskrnl/hl/amd64/cpufunc.c +++ b/xtoskrnl/hl/amd64/cpufunc.c @@ -9,6 +9,48 @@ #include "xtkmapi.h" +/** + * Retrieves a various amount of information about the CPU. + * + * @param Registers + * Supplies a pointer to the structure containing all the necessary registers and leafs for CPUID. + * + * @return TRUE if CPUID function could be executed, FALSE otherwise. + * + * @since XT 1.0 + */ +XTAPI +BOOLEAN +HlCpuId(IN OUT PCPUID_REGISTERS Registers) +{ + UINT32 MaxLeaf; + + /* Get highest function ID available */ + asm volatile("cpuid" + : "=a" (MaxLeaf) + : "a" (Registers->Leaf & 0x80000000) + : "rbx", "rcx", "rdx"); + + /* Check if CPU supports this command */ + if(Registers->Leaf > MaxLeaf) + { + /* Cannot call it, return FALSE */ + return FALSE; + } + + /* Execute CPUID function */ + asm volatile("cpuid" + : "=a" (Registers->Eax), + "=b" (Registers->Ebx), + "=c" (Registers->Ecx), + "=d" (Registers->Edx) + : "a" (Registers->Leaf), + "c" (Registers->SubLeaf)); + + /* Return TRUE */ + return TRUE; +} + /** * Reads the data from the specified I/O port. * @@ -50,8 +92,7 @@ HlIoPortOutByte(IN USHORT Port, { asm volatile("outb %0, %1" : - : - "a"(Value), + : "a"(Value), "Nd"(Port)); } @@ -68,12 +109,9 @@ HlReadCR0() { ULONG_PTR Value; asm volatile("mov %%cr0, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -90,12 +128,9 @@ HlReadCR2() { ULONG_PTR Value; asm volatile("mov %%cr2, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -112,12 +147,9 @@ HlReadCR3() { ULONG_PTR Value; asm volatile("mov %%cr3, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -134,12 +166,9 @@ HlReadCR4() { ULONG_PTR Value; asm volatile("mov %%cr4, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -156,12 +185,9 @@ HlReadCR8() { ULONG_PTR Value; asm volatile("mov %%cr8, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -181,10 +207,8 @@ HlWriteCR0(UINT_PTR Data) { asm volatile("mov %0, %%cr0" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } /** @@ -203,10 +227,8 @@ HlWriteCR2(UINT_PTR Data) { asm volatile("mov %0, %%cr2" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } /** @@ -225,10 +247,8 @@ HlWriteCR3(UINT_PTR Data) { asm volatile("mov %0, %%cr3" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } /** @@ -247,10 +267,8 @@ HlWriteCR4(UINT_PTR Data) { asm volatile("mov %0, %%cr4" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } /** @@ -269,8 +287,6 @@ HlWriteCR8(UINT_PTR Data) { asm volatile("mov %0, %%cr8" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } diff --git a/xtoskrnl/hl/i686/cpufunc.c b/xtoskrnl/hl/i686/cpufunc.c index 7ffcb82..ee4626a 100644 --- a/xtoskrnl/hl/i686/cpufunc.c +++ b/xtoskrnl/hl/i686/cpufunc.c @@ -9,6 +9,48 @@ #include "xtkmapi.h" +/** + * Retrieves a various amount of information about the CPU. + * + * @param Registers + * Supplies a pointer to the structure containing all the necessary registers and leafs for CPUID. + * + * @return TRUE if CPUID function could be executed, FALSE otherwise. + * + * @since XT 1.0 + */ +XTAPI +BOOLEAN +HlCpuId(IN OUT PCPUID_REGISTERS Registers) +{ + UINT32 MaxLeaf; + + /* Get highest function ID available */ + asm volatile("cpuid" + : "=a" (MaxLeaf) + : "a" (Registers->Leaf & 0x80000000) + : "rbx", "rcx", "rdx"); + + /* Check if CPU supports this command */ + if(Registers->Leaf > MaxLeaf) + { + /* Cannot call it, return FALSE */ + return FALSE; + } + + /* Execute CPUID function */ + asm volatile("cpuid" + : "=a" (Registers->Eax), + "=b" (Registers->Ebx), + "=c" (Registers->Ecx), + "=d" (Registers->Edx) + : "a" (Registers->Leaf), + "c" (Registers->SubLeaf)); + + /* Return TRUE */ + return TRUE; +} + /** * Reads the data from the specified I/O port. * @@ -50,8 +92,7 @@ HlIoPortOutByte(IN USHORT Port, { asm volatile("outb %0, %1" : - : - "a"(Value), + : "a"(Value), "Nd"(Port)); } @@ -68,12 +109,9 @@ HlReadCR0() { ULONG_PTR Value; asm volatile("mov %%cr0, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -90,12 +128,9 @@ HlReadCR2() { ULONG_PTR Value; asm volatile("mov %%cr2, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -112,12 +147,9 @@ HlReadCR3() { ULONG_PTR Value; asm volatile("mov %%cr3, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -134,12 +166,9 @@ HlReadCR4() { ULONG_PTR Value; asm volatile("mov %%cr4, %0" + : "=r" (Value) : - "=r" - (Value) - : - : - "memory"); + : "memory"); return Value; } @@ -159,10 +188,8 @@ HlWriteCR0(UINT_PTR Data) { asm volatile("mov %0, %%cr0" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } /** @@ -181,10 +208,8 @@ HlWriteCR2(UINT_PTR Data) { asm volatile("mov %0, %%cr2" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } /** @@ -203,10 +228,8 @@ HlWriteCR3(UINT_PTR Data) { asm volatile("mov %0, %%cr3" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); } /** @@ -225,8 +248,6 @@ HlWriteCR4(UINT_PTR Data) { asm volatile("mov %0, %%cr4" : - : - "r"(Data) - : - "memory"); + : "r"(Data) + : "memory"); }