From 35aa514f956527fbdc6e48777fee1dd2b43bf082 Mon Sep 17 00:00:00 2001
From: belliash <belliash@codingworkshop.eu.org>
Date: Tue, 24 Jan 2023 19:27:18 +0100
Subject: [PATCH] Implement HlLoadSegment() intrinsics routine

---
 sdk/xtdk/amd64/hlfuncs.h    |  5 ++++
 sdk/xtdk/i686/hlfuncs.h     |  5 ++++
 xtoskrnl/hl/amd64/cpufunc.c | 53 +++++++++++++++++++++++++++++++++++++
 xtoskrnl/hl/i686/cpufunc.c  | 53 +++++++++++++++++++++++++++++++++++++
 4 files changed, 116 insertions(+)

diff --git a/sdk/xtdk/amd64/hlfuncs.h b/sdk/xtdk/amd64/hlfuncs.h
index 2a88cc3..8307214 100644
--- a/sdk/xtdk/amd64/hlfuncs.h
+++ b/sdk/xtdk/amd64/hlfuncs.h
@@ -63,6 +63,11 @@ XTCDECL
 VOID
 HlLoadGlobalDescriptorTable(IN PVOID Source);
 
+XTCDECL
+VOID
+HlLoadSegment(IN USHORT Segment,
+              IN PVOID Source);
+
 XTCDECL
 VOID
 HlLoadTaskRegister(USHORT Source);
diff --git a/sdk/xtdk/i686/hlfuncs.h b/sdk/xtdk/i686/hlfuncs.h
index b0f919d..70ed65f 100644
--- a/sdk/xtdk/i686/hlfuncs.h
+++ b/sdk/xtdk/i686/hlfuncs.h
@@ -63,6 +63,11 @@ XTCDECL
 VOID
 HlLoadGlobalDescriptorTable(IN PVOID Source);
 
+XTCDECL
+VOID
+HlLoadSegment(IN USHORT Segment,
+              IN PVOID Source);
+
 XTCDECL
 VOID
 HlLoadTaskRegister(USHORT Source);
diff --git a/xtoskrnl/hl/amd64/cpufunc.c b/xtoskrnl/hl/amd64/cpufunc.c
index 9209f97..65ff365 100644
--- a/xtoskrnl/hl/amd64/cpufunc.c
+++ b/xtoskrnl/hl/amd64/cpufunc.c
@@ -256,6 +256,59 @@ HlLoadGlobalDescriptorTable(IN PVOID Source)
                  : "memory");
 }
 
+/**
+ * Loads source data into specified segment.
+ *
+ * @param Segment
+ *        Supplies a segment identification.
+ *
+ * @param Source
+ *        Supplies a pointer to the memory area containing data that will be loaded into specified segment.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HlLoadSegment(IN USHORT Segment,
+              IN PVOID Source)
+{
+    switch(Segment)
+    {
+        case SEGMENT_CS:
+            asm volatile("movl %0, %%cs"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_DS:
+            asm volatile("movl %0, %%ds"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_ES:
+            asm volatile("movl %0, %%es"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_FS:
+            asm volatile("movl %0, %%fs"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_GS:
+            asm volatile("movl %0, %%gs"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_SS:
+            asm volatile("movl %0, %%ss"
+                         :
+                         : "r" (Source));
+            break;
+    }
+}
+
 /**
  * Loads Task Register (TR) with a segment selector that points to TSS.
  *
diff --git a/xtoskrnl/hl/i686/cpufunc.c b/xtoskrnl/hl/i686/cpufunc.c
index cef442e..b1c2518 100644
--- a/xtoskrnl/hl/i686/cpufunc.c
+++ b/xtoskrnl/hl/i686/cpufunc.c
@@ -256,6 +256,59 @@ HlLoadGlobalDescriptorTable(IN PVOID Source)
                  : "memory");
 }
 
+/**
+ * Loads source data into specified segment.
+ *
+ * @param Segment
+ *        Supplies a segment identification.
+ *
+ * @param Source
+ *        Supplies a pointer to the memory area containing data that will be loaded into specified segment.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+HlLoadSegment(IN USHORT Segment,
+              IN PVOID Source)
+{
+    switch(Segment)
+    {
+        case SEGMENT_CS:
+            asm volatile("movl %0, %%cs"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_DS:
+            asm volatile("movl %0, %%ds"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_ES:
+            asm volatile("movl %0, %%es"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_FS:
+            asm volatile("movl %0, %%fs"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_GS:
+            asm volatile("movl %0, %%gs"
+                         :
+                         : "r" (Source));
+            break;
+        case SEGMENT_SS:
+            asm volatile("movl %0, %%ss"
+                         :
+                         : "r" (Source));
+            break;
+    }
+}
+
 /**
  * Loads Task Register (TR) with a segment selector that points to TSS.
  *