From 64b5de98c83f82f264e319f38174f775b1ad5606 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Fri, 27 Mar 2026 12:00:09 +0100 Subject: [PATCH 1/6] Move IRQ handling from kernel executive to hardware layer --- xtoskrnl/CMakeLists.txt | 2 +- xtoskrnl/hl/x86/pic.cc | 4 +-- xtoskrnl/includes/hl.hh | 1 + xtoskrnl/includes/{ke => hl}/irq.hh | 14 +++++----- xtoskrnl/includes/ke.hh | 1 - xtoskrnl/ke/amd64/irq.cc | 43 ----------------------------- xtoskrnl/ke/i686/irq.cc | 43 ----------------------------- 7 files changed, 11 insertions(+), 97 deletions(-) rename xtoskrnl/includes/{ke => hl}/irq.hh (62%) delete mode 100644 xtoskrnl/ke/amd64/irq.cc delete mode 100644 xtoskrnl/ke/i686/irq.cc diff --git a/xtoskrnl/CMakeLists.txt b/xtoskrnl/CMakeLists.txt index 1080ff6..fb2da17 100644 --- a/xtoskrnl/CMakeLists.txt +++ b/xtoskrnl/CMakeLists.txt @@ -20,6 +20,7 @@ list(APPEND XTOSKRNL_SOURCE ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/cpu.cc ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/pic.cc ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/ioport.cc + ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/irq.cc ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/runlevel.cc ${XTOSKRNL_SOURCE_DIR}/hl/acpi.cc ${XTOSKRNL_SOURCE_DIR}/hl/cport.cc @@ -31,7 +32,6 @@ list(APPEND XTOSKRNL_SOURCE ${XTOSKRNL_SOURCE_DIR}/kd/data.cc ${XTOSKRNL_SOURCE_DIR}/kd/dbgio.cc ${XTOSKRNL_SOURCE_DIR}/kd/exports.cc - ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/irq.cc ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/krnlinit.cc ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/kthread.cc ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/proc.cc diff --git a/xtoskrnl/hl/x86/pic.cc b/xtoskrnl/hl/x86/pic.cc index 8fefc6c..bfe0219 100644 --- a/xtoskrnl/hl/x86/pic.cc +++ b/xtoskrnl/hl/x86/pic.cc @@ -249,8 +249,8 @@ HL::Pic::InitializeApic(VOID) WriteApicRegister(APIC_LINT1, LvtRegister.Long); /* Register interrupt handlers */ - KE::Irq::SetInterruptHandler(APIC_VECTOR_SPURIOUS, (PVOID)HandleApicSpuriousService); - KE::Irq::SetInterruptHandler(PIC1_VECTOR_SPURIOUS, (PVOID)HandlePicSpuriousService); + HL::Irq::SetInterruptHandler(APIC_VECTOR_SPURIOUS, (PVOID)HandleApicSpuriousService); + HL::Irq::SetInterruptHandler(PIC1_VECTOR_SPURIOUS, (PVOID)HandlePicSpuriousService); /* Clear any pre-existing errors */ WriteApicRegister(APIC_ESR, 0); diff --git a/xtoskrnl/includes/hl.hh b/xtoskrnl/includes/hl.hh index fd76ffc..a3eda53 100644 --- a/xtoskrnl/includes/hl.hh +++ b/xtoskrnl/includes/hl.hh @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/xtoskrnl/includes/ke/irq.hh b/xtoskrnl/includes/hl/irq.hh similarity index 62% rename from xtoskrnl/includes/ke/irq.hh rename to xtoskrnl/includes/hl/irq.hh index 8817fe2..ac37a22 100644 --- a/xtoskrnl/includes/ke/irq.hh +++ b/xtoskrnl/includes/hl/irq.hh @@ -1,19 +1,19 @@ /** * PROJECT: ExectOS * COPYRIGHT: See COPYING.md in the top level directory - * FILE: xtoskrnl/includes/ke/irq.hh - * DESCRIPTION: Kernel interrupts support + * FILE: xtoskrnl/includes/hl/irq.hh + * DESCRIPTION: Interrupts support * DEVELOPERS: Aiken Harris */ -#ifndef __XTOSKRNL_KE_IRQ_HH -#define __XTOSKRNL_KE_IRQ_HH +#ifndef __XTOSKRNL_HL_IRQ_HH +#define __XTOSKRNL_HL_IRQ_HH #include -/* Kernel Library */ -namespace KE +/* Hardware Layer */ +namespace HL { class Irq { @@ -23,4 +23,4 @@ namespace KE }; } -#endif /* __XTOSKRNL_KE_IRQ_HH */ +#endif /* __XTOSKRNL_HL_IRQ_HH */ diff --git a/xtoskrnl/includes/ke.hh b/xtoskrnl/includes/ke.hh index 607e2e7..fa995d6 100644 --- a/xtoskrnl/includes/ke.hh +++ b/xtoskrnl/includes/ke.hh @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/xtoskrnl/ke/amd64/irq.cc b/xtoskrnl/ke/amd64/irq.cc deleted file mode 100644 index 209cd7c..0000000 --- a/xtoskrnl/ke/amd64/irq.cc +++ /dev/null @@ -1,43 +0,0 @@ -/** - * PROJECT: ExectOS - * COPYRIGHT: See COPYING.md in the top level directory - * FILE: xtoskrnl/ke/amd64/irq.cc - * DESCRIPTION: Kernel interrupts support for amd64 architecture - * DEVELOPERS: Rafal Kupiec - */ - -#include - - -/** - * Sets new interrupt handler for the existing IDT entry. - * - * @param HalVector - * Supplies the HAL vector number. - * - * @param Handler - * Supplies the new interrupt handler. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTAPI -VOID -KE::Irq::SetInterruptHandler(IN ULONG Vector, - IN PVOID Handler) -{ - PKPROCESSOR_BLOCK ProcessorBlock; - - /* Get current processor block */ - ProcessorBlock = KE::Processor::GetCurrentProcessorBlock(); - - /* Update interrupt handler */ - AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase, - Vector, - Handler, - KGDT_R0_CODE, - 0, - KIDT_ACCESS_RING0, - AMD64_INTERRUPT_GATE); -} diff --git a/xtoskrnl/ke/i686/irq.cc b/xtoskrnl/ke/i686/irq.cc deleted file mode 100644 index 9e33c7c..0000000 --- a/xtoskrnl/ke/i686/irq.cc +++ /dev/null @@ -1,43 +0,0 @@ -/** - * PROJECT: ExectOS - * COPYRIGHT: See COPYING.md in the top level directory - * FILE: xtoskrnl/ke/i686/irq.cc - * DESCRIPTION: Kernel interrupts support for i686 architecture - * DEVELOPERS: Rafal Kupiec - */ - -#include - - -/** - * Sets new interrupt handler for the existing IDT entry. - * - * @param HalVector - * Supplies the HAL vector number. - * - * @param Handler - * Supplies the new interrupt handler. - * - * @return This routine does not return any value. - * - * @since XT 1.0 - */ -XTAPI -VOID -KE::Irq::SetInterruptHandler(IN ULONG Vector, - IN PVOID Handler) -{ - PKPROCESSOR_BLOCK ProcessorBlock; - - /* Get current processor block */ - ProcessorBlock = KE::Processor::GetCurrentProcessorBlock(); - - /* Update interrupt handler */ - AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase, - Vector, - Handler, - KGDT_R0_CODE, - 0, - KIDT_ACCESS_RING0, - I686_INTERRUPT_GATE); -} From a64aa83eb84d20d592c0d06cd0d234f6bee888a2 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Fri, 27 Mar 2026 13:00:13 +0100 Subject: [PATCH 2/6] Provide implementation for HL::Irq --- xtoskrnl/hl/amd64/irq.cc | 44 ++++++++++++++++++++++++++++++++++++++++ xtoskrnl/hl/i686/irq.cc | 44 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 xtoskrnl/hl/amd64/irq.cc create mode 100644 xtoskrnl/hl/i686/irq.cc diff --git a/xtoskrnl/hl/amd64/irq.cc b/xtoskrnl/hl/amd64/irq.cc new file mode 100644 index 0000000..c071987 --- /dev/null +++ b/xtoskrnl/hl/amd64/irq.cc @@ -0,0 +1,44 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/hl/amd64/irq.cc + * DESCRIPTION: Interrupts support for amd64 architecture + * DEVELOPERS: Rafal Kupiec + * Aiken Harris + */ + +#include + + +/** + * Sets new interrupt handler for the existing IDT entry. + * + * @param HalVector + * Supplies the HAL vector number. + * + * @param Handler + * Supplies the new interrupt handler. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +HL::Irq::SetInterruptHandler(IN ULONG Vector, + IN PVOID Handler) +{ + PKPROCESSOR_BLOCK ProcessorBlock; + + /* Get current processor block */ + ProcessorBlock = KE::Processor::GetCurrentProcessorBlock(); + + /* Update interrupt handler */ + AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase, + Vector, + Handler, + KGDT_R0_CODE, + 0, + KIDT_ACCESS_RING0, + AMD64_INTERRUPT_GATE); +} diff --git a/xtoskrnl/hl/i686/irq.cc b/xtoskrnl/hl/i686/irq.cc new file mode 100644 index 0000000..cd658ec --- /dev/null +++ b/xtoskrnl/hl/i686/irq.cc @@ -0,0 +1,44 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/hl/i686/irq.cc + * DESCRIPTION: Interrupts support for i686 architecture + * DEVELOPERS: Rafal Kupiec + * Aiken Harris + */ + +#include + + +/** + * Sets new interrupt handler for the existing IDT entry. + * + * @param HalVector + * Supplies the HAL vector number. + * + * @param Handler + * Supplies the new interrupt handler. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +HL::Irq::SetInterruptHandler(IN ULONG Vector, + IN PVOID Handler) +{ + PKPROCESSOR_BLOCK ProcessorBlock; + + /* Get current processor block */ + ProcessorBlock = KE::Processor::GetCurrentProcessorBlock(); + + /* Update interrupt handler */ + AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase, + Vector, + Handler, + KGDT_R0_CODE, + 0, + KIDT_ACCESS_RING0, + I686_INTERRUPT_GATE); +} From 9c449bed43d47c99c0dab798bfcb27fc6ae9d4df Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Fri, 27 Mar 2026 19:16:16 +0100 Subject: [PATCH 3/6] Initialize IDT with specific trap handlers for each vector --- xtoskrnl/ar/amd64/archsup.S | 9 +++++++++ xtoskrnl/ar/amd64/procsup.cc | 2 +- xtoskrnl/ar/i686/archsup.S | 11 ++++++++++- xtoskrnl/ar/i686/procsup.cc | 2 +- xtoskrnl/includes/ar/amd64/procsup.hh | 3 +++ xtoskrnl/includes/ar/i686/procsup.hh | 3 +++ 6 files changed, 27 insertions(+), 3 deletions(-) diff --git a/xtoskrnl/ar/amd64/archsup.S b/xtoskrnl/ar/amd64/archsup.S index 481cd53..674f745 100644 --- a/xtoskrnl/ar/amd64/archsup.S +++ b/xtoskrnl/ar/amd64/archsup.S @@ -187,3 +187,12 @@ KernelModeReturn$\Vector: ArCreateTrapHandler 0x\i\j .endr .endr + +/* Define array of pointers to the trap handlers */ +.global ArTrapEntry +ArTrapEntry: +.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .quad ArTrap0x\i\j + .endr +.endr diff --git a/xtoskrnl/ar/amd64/procsup.cc b/xtoskrnl/ar/amd64/procsup.cc index 29720e0..d20d3a6 100644 --- a/xtoskrnl/ar/amd64/procsup.cc +++ b/xtoskrnl/ar/amd64/procsup.cc @@ -249,7 +249,7 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock) for(Vector = 0; Vector < IDT_ENTRIES; Vector++) { /* Set the IDT to handle unexpected interrupts */ - SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); } /* Setup IDT handlers for known interrupts and traps */ diff --git a/xtoskrnl/ar/i686/archsup.S b/xtoskrnl/ar/i686/archsup.S index 4e73bc1..d5e20fe 100644 --- a/xtoskrnl/ar/i686/archsup.S +++ b/xtoskrnl/ar/i686/archsup.S @@ -82,7 +82,7 @@ _ArTrap\Vector: jmp UserMode$\Vector KernelMode$\Vector: - /* Save kernel stack pointer (SS:ESP) as CPU did not push them */ + /* Save kernel stack pointer (SS:ESP) */ movl %ss, %eax mov %eax, TrapSegSs(%ebp) lea TrapEsp(%ebp), %eax @@ -133,3 +133,12 @@ KernelModeReturn$\Vector: ArCreateTrapHandler 0x\i\j .endr .endr + +/* Define array of pointers to the trap handlers */ +.global ArTrapEntry +ArTrapEntry: +.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .long ArTrap0x\i\j + .endr +.endr diff --git a/xtoskrnl/ar/i686/procsup.cc b/xtoskrnl/ar/i686/procsup.cc index 35f645e..b8b8da2 100644 --- a/xtoskrnl/ar/i686/procsup.cc +++ b/xtoskrnl/ar/i686/procsup.cc @@ -242,7 +242,7 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock) for(Vector = 0; Vector < IDT_ENTRIES; Vector++) { /* Set the IDT to handle unexpected interrupts */ - SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrap0xFF, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE); } /* Setup IDT handlers for known interrupts and traps */ diff --git a/xtoskrnl/includes/ar/amd64/procsup.hh b/xtoskrnl/includes/ar/amd64/procsup.hh index 4cad247..d663596 100644 --- a/xtoskrnl/includes/ar/amd64/procsup.hh +++ b/xtoskrnl/includes/ar/amd64/procsup.hh @@ -12,6 +12,9 @@ #include +/* External array of pointers to the trap handlers */ +XTCLINK ULONG_PTR ArTrapEntry[256]; + /* Architecture-specific Library */ namespace AR { diff --git a/xtoskrnl/includes/ar/i686/procsup.hh b/xtoskrnl/includes/ar/i686/procsup.hh index 2b4931f..de4de60 100644 --- a/xtoskrnl/includes/ar/i686/procsup.hh +++ b/xtoskrnl/includes/ar/i686/procsup.hh @@ -12,6 +12,9 @@ #include +/* External array of pointers to the trap handlers */ +XTCLINK ULONG_PTR ArTrapEntry[256]; + /* Architecture-specific Library */ namespace AR { From 0c1733738814f09cfee35498b7dd23521fe3b975 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Fri, 27 Mar 2026 19:23:37 +0100 Subject: [PATCH 4/6] Fix symbol naming convention for i686 trap handlers --- xtoskrnl/ar/i686/archsup.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/xtoskrnl/ar/i686/archsup.S b/xtoskrnl/ar/i686/archsup.S index d5e20fe..df49f79 100644 --- a/xtoskrnl/ar/i686/archsup.S +++ b/xtoskrnl/ar/i686/archsup.S @@ -135,10 +135,10 @@ KernelModeReturn$\Vector: .endr /* Define array of pointers to the trap handlers */ -.global ArTrapEntry -ArTrapEntry: +.global _ArTrapEntry +_ArTrapEntry: .irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F - .long ArTrap0x\i\j + .long _ArTrap0x\i\j .endr .endr From 32d3672a51c417d7f6fd7f442afb616f3760f457 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Fri, 27 Mar 2026 20:42:41 +0100 Subject: [PATCH 5/6] Generate distinct handlers for CPU traps and hardware interrupts --- xtoskrnl/ar/amd64/archsup.S | 60 +++++++---- xtoskrnl/ar/amd64/procsup.cc | 51 +++++----- xtoskrnl/ar/i686/archsup.S | 60 +++++++---- xtoskrnl/ar/i686/procsup.cc | 55 ++++++----- xtoskrnl/includes/ar/amd64/assembly.hh | 130 +----------------------- xtoskrnl/includes/ar/amd64/procsup.hh | 3 - xtoskrnl/includes/ar/i686/assembly.hh | 131 +------------------------ xtoskrnl/includes/ar/i686/procsup.hh | 3 - 8 files changed, 150 insertions(+), 343 deletions(-) diff --git a/xtoskrnl/ar/amd64/archsup.S b/xtoskrnl/ar/amd64/archsup.S index 674f745..3853dc7 100644 --- a/xtoskrnl/ar/amd64/archsup.S +++ b/xtoskrnl/ar/amd64/archsup.S @@ -13,20 +13,29 @@ /** - * Creates a trap handler for the specified vector. + * Creates a trap or interrupt handler for the specified vector. * * @param Vector - * Supplies a trap vector number. + * Supplies a trap/interrupt vector number. + * + * @param Type + * Specifies whether the handler is designed to handle an interrupt or a trap. * * @return This macro does not return any value. * * @since XT 1.0 */ -.macro ArCreateTrapHandler Vector -.global ArTrap\Vector -ArTrap\Vector: - /* Push fake error code for non-error vectors */ - .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30 +.macro ArCreateTrapHandler Vector Type +.global Ar\Type\Vector +Ar\Type\Vector: + /* Check handler type */ + .ifc \Type,Trap + /* Push fake error code for non-error vector traps */ + .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30 + push $0 + .endif + .else + /* Push fake error code for interrupts */ push $0 .endif @@ -106,30 +115,37 @@ ArTrap\Vector: mov %cs, %ax and $3, %al mov %al, TrapPreviousMode(%rbp) - jz KernelMode$\Vector + jz KernelMode\Type\Vector swapgs - jmp UserMode$\Vector + jmp UserMode\Type\Vector -KernelMode$\Vector: +KernelMode\Type\Vector: /* Save kernel stack pointer (SS:RSP) */ movl %ss, %eax mov %eax, TrapSegSs(%rbp) lea TRAP_FRAME_SIZE(%rbp), %rax mov %rax, TrapRsp(%rbp) -UserMode$\Vector: - /* Push Frame Pointer, clear direction flag and pass to trap dispatcher */ +UserMode\Type\Vector: + /* Push Frame Pointer and clear direction flag */ mov %rsp, %rcx cld - call ArDispatchTrap + + .ifc \Type,Trap + /* Pass to the trap dispatcher */ + call ArDispatchTrap + .else + /* Pass to the interrupt dispatcher */ + call ArDispatchTrap + .endif /* Test previous mode and swapgs if needed */ testb $1, TrapPreviousMode(%rbp) - jz KernelModeReturn$\Vector + jz KernelModeReturn\Type\Vector cli swapgs -KernelModeReturn$\Vector: +KernelModeReturn\Type\Vector: /* Restore XMM registers */ movdqa TrapXmm0(%rbp), %xmm0 movdqa TrapXmm1(%rbp), %xmm1 @@ -181,10 +197,20 @@ KernelModeReturn$\Vector: iretq .endm -/* Populate common trap handlers */ +/* Populate common interrupt and trap handlers */ .irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F - ArCreateTrapHandler 0x\i\j + ArCreateTrapHandler 0x\i\j Interrupt + ArCreateTrapHandler 0x\i\j Trap + .endr +.endr + +/* Define array of pointers to the interrupt handlers */ +.global ArInterruptEntry +ArInterruptEntry: +.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .quad ArInterrupt0x\i\j .endr .endr diff --git a/xtoskrnl/ar/amd64/procsup.cc b/xtoskrnl/ar/amd64/procsup.cc index d20d3a6..3a8c56e 100644 --- a/xtoskrnl/ar/amd64/procsup.cc +++ b/xtoskrnl/ar/amd64/procsup.cc @@ -249,34 +249,35 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock) for(Vector = 0; Vector < IDT_ENTRIES; Vector++) { /* Set the IDT to handle unexpected interrupts */ - SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArInterruptEntry[Vector], KGDT_R0_CODE, + KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); } /* Setup IDT handlers for known interrupts and traps */ - SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrap0x1F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrap0x2F, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrap0xE1, KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrapEntry[0x00], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrapEntry[0x01], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrapEntry[0x02], KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrapEntry[0x03], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrapEntry[0x04], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrapEntry[0x05], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrapEntry[0x06], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrapEntry[0x07], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrapEntry[0x08], KGDT_R0_CODE, KIDT_IST_PANIC, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrapEntry[0x09], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrapEntry[0x0A], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrapEntry[0x0B], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrapEntry[0x0C], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrapEntry[0x0D], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrapEntry[0x0E], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrapEntry[0x10], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrapEntry[0x11], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrapEntry[0x12], KGDT_R0_CODE, KIDT_IST_MCA, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrapEntry[0x13], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x1F, (PVOID)ArTrapEntry[0x1F], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrapEntry[0x2C], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrapEntry[0x2D], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING3, AMD64_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2F, (PVOID)ArTrapEntry[0x2F], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0xE1, (PVOID)ArTrapEntry[0xE1], KGDT_R0_CODE, KIDT_IST_RESERVED, KIDT_ACCESS_RING0, AMD64_INTERRUPT_GATE); } /** diff --git a/xtoskrnl/ar/i686/archsup.S b/xtoskrnl/ar/i686/archsup.S index df49f79..adae8d8 100644 --- a/xtoskrnl/ar/i686/archsup.S +++ b/xtoskrnl/ar/i686/archsup.S @@ -13,20 +13,29 @@ /** - * This macro creates a trap handler for the specified vector. + * Creates a trap or interrupt handler for the specified vector. * * @param Vector - * Supplies a trap vector number. + * Supplies a trap/interrupt vector number. + * + * @param Type + * Specifies whether the handler is designed to handle an interrupt or a trap. * * @return This macro does not return any value. * * @since XT 1.0 */ -.macro ArCreateTrapHandler Vector -.global _ArTrap\Vector -_ArTrap\Vector: - /* Push fake error code for non-error vectors */ - .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30 +.macro ArCreateTrapHandler Vector Type +.global _Ar\Type\Vector +_Ar\Type\Vector: + /* Check handler type */ + .ifc \Type,Trap + /* Push fake error code for non-error vector traps */ + .if \Vector != 8 && \Vector != 10 && \Vector != 11 && \Vector != 12 && \Vector != 13 && \Vector != 14 && \Vector != 17 && \Vector != 30 + push $0 + .endif + .else + /* Push fake error code for interrupts */ push $0 .endif @@ -77,33 +86,40 @@ _ArTrap\Vector: mov %cs, %ax and $3, %al mov %al, TrapPreviousMode(%ebp) - jz KernelMode$\Vector + jz KernelMode\Type\Vector swapgs - jmp UserMode$\Vector + jmp UserMode\Type\Vector -KernelMode$\Vector: +KernelMode\Type\Vector: /* Save kernel stack pointer (SS:ESP) */ movl %ss, %eax mov %eax, TrapSegSs(%ebp) lea TrapEsp(%ebp), %eax mov %eax, TrapEsp(%ebp) -UserMode$\Vector: - /* Push Frame Pointer, clear direction flag and pass to trap dispatcher */ +UserMode\Type\Vector: + /* Push Frame Pointer and clear direction flag */ push %esp cld - call _ArDispatchTrap + + .ifc \Type,Trap + /* Pass to the trap dispatcher */ + call _ArDispatchTrap + .else + /* Pass to the interrupt dispatcher */ + call _ArDispatchTrap + .endif /* Clean up the stack */ add $4, %esp /* Test previous mode and swapgs if needed */ testb $1, TrapPreviousMode(%ebp) - jz KernelModeReturn$\Vector + jz KernelModeReturn\Type\Vector cli swapgs -KernelModeReturn$\Vector: +KernelModeReturn\Type\Vector: /* Restore segment selectors */ mov TrapSegDs(%ebp), %ds mov TrapSegEs(%ebp), %es @@ -127,10 +143,20 @@ KernelModeReturn$\Vector: iretl .endm -/* Populate common trap handlers */ +/* Populate common interrupt and trap handlers */ .irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F - ArCreateTrapHandler 0x\i\j + ArCreateTrapHandler 0x\i\j Interrupt + ArCreateTrapHandler 0x\i\j Trap + .endr +.endr + +/* Define array of pointers to the interrupt handlers */ +.global _ArInterruptEntry +_ArInterruptEntry: +.irp i,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .irp j,0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F + .long _ArInterrupt0x\i\j .endr .endr diff --git a/xtoskrnl/ar/i686/procsup.cc b/xtoskrnl/ar/i686/procsup.cc index b8b8da2..8709598 100644 --- a/xtoskrnl/ar/i686/procsup.cc +++ b/xtoskrnl/ar/i686/procsup.cc @@ -242,34 +242,35 @@ AR::ProcSup::InitializeIdt(IN PKPROCESSOR_BLOCK ProcessorBlock) for(Vector = 0; Vector < IDT_ENTRIES; Vector++) { /* Set the IDT to handle unexpected interrupts */ - SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArTrapEntry[Vector], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, Vector, (PVOID)ArInterruptEntry[Vector], + KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE); } /* Setup IDT handlers for known interrupts and traps */ - SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrap0x00, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrap0x01, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrap0x02, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrap0x03, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrap0x04, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrap0x05, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrap0x06, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrap0x07, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrap0x08, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrap0x09, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrap0x0A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrap0x0B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrap0x0C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrap0x0D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrap0x0E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrap0x10, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrap0x11, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrap0x12, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrap0x13, KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrap0x2A, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrap0x2B, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrap0x2C, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrap0x2D, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); - SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrap0x2E, KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x00, (PVOID)ArTrapEntry[0x00], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x01, (PVOID)ArTrapEntry[0x01], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x02, (PVOID)ArTrapEntry[0x02], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_INTERRUPT_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x03, (PVOID)ArTrapEntry[0x03], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x04, (PVOID)ArTrapEntry[0x04], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x05, (PVOID)ArTrapEntry[0x05], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x06, (PVOID)ArTrapEntry[0x06], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x07, (PVOID)ArTrapEntry[0x07], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x08, (PVOID)ArTrapEntry[0x08], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x09, (PVOID)ArTrapEntry[0x09], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0A, (PVOID)ArTrapEntry[0x0A], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0B, (PVOID)ArTrapEntry[0x0B], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0C, (PVOID)ArTrapEntry[0x0C], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0D, (PVOID)ArTrapEntry[0x0D], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x0E, (PVOID)ArTrapEntry[0x0E], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x10, (PVOID)ArTrapEntry[0x10], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x11, (PVOID)ArTrapEntry[0x11], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x12, (PVOID)ArTrapEntry[0x12], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x13, (PVOID)ArTrapEntry[0x13], KGDT_R0_CODE, 0, KIDT_ACCESS_RING0, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2A, (PVOID)ArTrapEntry[0x2A], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2B, (PVOID)ArTrapEntry[0x2B], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2C, (PVOID)ArTrapEntry[0x2C], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2D, (PVOID)ArTrapEntry[0x2D], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); + SetIdtGate(ProcessorBlock->IdtBase, 0x2E, (PVOID)ArTrapEntry[0x2E], KGDT_R0_CODE, 0, KIDT_ACCESS_RING3, I686_TRAP_GATE); } /** @@ -506,7 +507,7 @@ AR::ProcSup::SetDoubleFaultTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock, Tss->CR3 = CpuFunc::ReadControlRegister(3); Tss->Esp = (ULONG_PTR)KernelFaultStack; Tss->Esp0 = (ULONG_PTR)KernelFaultStack; - Tss->Eip = PtrToUlong(ArTrap0x08); + Tss->Eip = PtrToUlong(ArTrapEntry[0x08]); Tss->Cs = KGDT_R0_CODE; Tss->Ds = KGDT_R3_DATA | RPL_MASK; Tss->Es = KGDT_R3_DATA | RPL_MASK; @@ -720,7 +721,7 @@ AR::ProcSup::SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock Tss->CR3 = CpuFunc::ReadControlRegister(3); Tss->Esp = (ULONG_PTR)KernelFaultStack; Tss->Esp0 = (ULONG_PTR)KernelFaultStack; - Tss->Eip = PtrToUlong(ArTrap0x02); + Tss->Eip = PtrToUlong(ArTrapEntry[0x02]); Tss->Cs = KGDT_R0_CODE; Tss->Ds = KGDT_R3_DATA | RPL_MASK; Tss->Es = KGDT_R3_DATA | RPL_MASK; diff --git a/xtoskrnl/includes/ar/amd64/assembly.hh b/xtoskrnl/includes/ar/amd64/assembly.hh index f9f7274..69355f9 100644 --- a/xtoskrnl/includes/ar/amd64/assembly.hh +++ b/xtoskrnl/includes/ar/amd64/assembly.hh @@ -15,9 +15,14 @@ /* TrampolineEnableXpa end address to calculate trampoline size */ XTCLINK PVOID ArEnableExtendedPhysicalAddressingEnd[]; +/* External array of pointers to the interrupt handlers */ +XTCLINK ULONG_PTR ArInterruptEntry[256]; + /* TrampolineApStartup end address to calculate trampoline size */ XTCLINK PVOID ArStartApplicationProcessorEnd[]; +/* External array of pointers to the trap handlers */ +XTCLINK ULONG_PTR ArTrapEntry[256]; /* Forward reference for assembler code */ XTCLINK @@ -30,129 +35,4 @@ XTCDECL VOID ArStartApplicationProcessor(VOID); -XTCLINK -XTCDECL -VOID -ArTrap0x00(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x01(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x02(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x03(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x04(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x05(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x06(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x07(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x08(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x09(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0A(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0B(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0C(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0D(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0E(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x10(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x11(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x12(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x13(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x1F(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2C(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2D(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2F(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0xE1(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0xFF(VOID); - #endif /* __XTOSKRNL_AR_ASSEMBLY_HH */ diff --git a/xtoskrnl/includes/ar/amd64/procsup.hh b/xtoskrnl/includes/ar/amd64/procsup.hh index d663596..4cad247 100644 --- a/xtoskrnl/includes/ar/amd64/procsup.hh +++ b/xtoskrnl/includes/ar/amd64/procsup.hh @@ -12,9 +12,6 @@ #include -/* External array of pointers to the trap handlers */ -XTCLINK ULONG_PTR ArTrapEntry[256]; - /* Architecture-specific Library */ namespace AR { diff --git a/xtoskrnl/includes/ar/i686/assembly.hh b/xtoskrnl/includes/ar/i686/assembly.hh index f2a7a2e..1fab319 100644 --- a/xtoskrnl/includes/ar/i686/assembly.hh +++ b/xtoskrnl/includes/ar/i686/assembly.hh @@ -12,9 +12,14 @@ #include +/* External array of pointers to the interrupt handlers */ +XTCLINK ULONG_PTR ArInterruptEntry[256]; + /* TrampolineApStartup end address to calculate trampoline size */ XTCLINK PVOID ArStartApplicationProcessorEnd[]; +/* External array of pointers to the trap handlers */ +XTCLINK ULONG_PTR ArTrapEntry[256]; /* Forward reference for assembler code */ XTCLINK @@ -22,130 +27,4 @@ XTCDECL VOID ArStartApplicationProcessor(VOID); -XTCLINK -XTCDECL -VOID -ArTrap0x00(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x01(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x02(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x03(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x04(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x05(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x06(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x07(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x08(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x09(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0A(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0B(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0C(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0D(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x0E(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x10(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x11(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x12(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x13(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2A(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2B(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2C(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2D(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0x2E(VOID); - -XTCLINK -XTCDECL -VOID -ArTrap0xFF(VOID); - - #endif /* __XTOSKRNL_AR_ASSEMBLY_HH */ diff --git a/xtoskrnl/includes/ar/i686/procsup.hh b/xtoskrnl/includes/ar/i686/procsup.hh index de4de60..2b4931f 100644 --- a/xtoskrnl/includes/ar/i686/procsup.hh +++ b/xtoskrnl/includes/ar/i686/procsup.hh @@ -12,9 +12,6 @@ #include -/* External array of pointers to the trap handlers */ -XTCLINK ULONG_PTR ArTrapEntry[256]; - /* Architecture-specific Library */ namespace AR { From a0b09380991df5c1bfc4dc583515c3009283f6f0 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Fri, 27 Mar 2026 22:07:20 +0100 Subject: [PATCH 6/6] Remove unused header --- xtoskrnl/includes/ke/info.hh | 27 --------------------------- 1 file changed, 27 deletions(-) delete mode 100644 xtoskrnl/includes/ke/info.hh diff --git a/xtoskrnl/includes/ke/info.hh b/xtoskrnl/includes/ke/info.hh deleted file mode 100644 index 4ff789e..0000000 --- a/xtoskrnl/includes/ke/info.hh +++ /dev/null @@ -1,27 +0,0 @@ -/** - * PROJECT: ExectOS - * COPYRIGHT: See COPYING.md in the top level directory - * FILE: xtoskrnl/includes/ke/info.hh - * DESCRIPTION: Generic kernel information support - * DEVELOPERS: Aiken Harris - */ - -#ifndef __XTOSKRNL_KE_INFO_HH -#define __XTOSKRNL_KE_INFO_HH - -#include - - -/* Kernel Library */ -namespace KE -{ - class Info - { - public: - STATIC XTAPI SYSTEM_FIRMWARE_TYPE GetFirmwareType(VOID); - STATIC XTAPI XTSTATUS GetKernelParameter(IN PCWSTR ParameterName, - OUT PCWSTR *Parameter); - }; -} - -#endif /* __XTOSKRNL_KE_INFO_HH */