Migrate MM subsystem to C++

2025-09-15 22:15:07 +02:00
parent 3e097c260d
commit 404595801d
26 changed files with 919 additions and 487 deletions
--- a/xtoskrnl/mm/amd64/globals.c
+++ b/xtoskrnl/mm/amd64/globals.c
@@ -1,26 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/mm/amd64/globals.c
- * DESCRIPTION:     AMD64-specific global variables for the Memory Manager
- * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
- */
-
-#include <xtos.h>
-
-
-/* Page mapping routines for systems using 4-level paging (PML4) */
-CMMPAGEMAP_ROUTINES MmpPml4Routines = {
-    .ClearPte = MmpClearPte,
-    .PteValid = MmpPteValid,
-    .SetPteCaching = MmpSetPteCaching,
-    .SetPte = MmpSetPte,
-};
-
-/* Page mapping routines for systems using 5-level paging (PML5) */
-CMMPAGEMAP_ROUTINES MmpPml5Routines = {
-    .ClearPte = MmpClearPte,
-    .PteValid = MmpPteValid,
-    .SetPteCaching = MmpSetPteCaching,
-    .SetPte = MmpSetPte,
-};
--- a/xtoskrnl/mm/amd64/init.c
+++ b/xtoskrnl/mm/amd64/init.c
@@ -1,75 +0,0 @@
-/**
- * PROJECT:         ExectOS
- * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/mm/amd64/init.c
- * DESCRIPTION:     Architecture specific Memory Manager initialization routines
- * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
- *                  Aiken Harris <harraiken91@gmail.com>
- */
-
-#include <xtos.h>
-
-
-/**
- * Detects if eXtended Physical Addressing (XPA) is enabled and initializes page map support.
- *
- * @return This routine does not return any value.
- *
- * @since XT 1.0
- */
-XTAPI
-VOID
-MmInitializePageMapSupport(VOID)
-{
-    /* Check if XPA is enabled */
-    if(MmpGetExtendedPhysicalAddressingStatus())
-    {
-        /* XPA enabled, use LA57 paging (PML5) */
-        MmpPageMapRoutines = &MmpPml5Routines;
-
-        /* Set PML5 page map information */
-        MmpPageMapInfo.Xpa = TRUE;
-
-        /* Set PML5 base addresses */
-        MmpPageMapInfo.PteBase = MM_PTE_LA57_BASE;
-        MmpPageMapInfo.PdeBase = MM_PDE_LA57_BASE;
-        MmpPageMapInfo.PpeBase = MM_PPE_LA57_BASE;
-        MmpPageMapInfo.PxeBase = MM_PXE_LA57_BASE;
-        MmpPageMapInfo.P5eBase = MM_P5E_LA57_BASE;
-
-        /* PML5 use 57-bit virtual addresses */
-        MmpPageMapInfo.VaBits = 57;
-    }
-    else
-    {
-        /* XPA disabled, use LA48 paging (PML4) */
-        MmpPageMapRoutines = &MmpPml4Routines;
-
-        /* Set PML4 page map information */
-        MmpPageMapInfo.Xpa = FALSE;
-
-        /* Set PML4 base addresses */
-        MmpPageMapInfo.PteBase = MM_PTE_BASE;
-        MmpPageMapInfo.PdeBase = MM_PDE_BASE;
-        MmpPageMapInfo.PpeBase = MM_PPE_BASE;
-        MmpPageMapInfo.PxeBase = MM_PXE_BASE;
-        MmpPageMapInfo.P5eBase = 0x0;
-
-        /* PML use 48-bit virtual addresses */
-        MmpPageMapInfo.VaBits = 48;
-    }
-}
-
-/**
- * Performs architecture specific initialization of the XTOS Memory Manager.
- *
- * @return This routine does not return any value.
- *
- * @since XT 1.0
- */
-XTAPI
-VOID
-MmpInitializeArchitecture(VOID)
-{
-    UNIMPLEMENTED;
-}
--- a/xtoskrnl/mm/amd64/init.cc
+++ b/xtoskrnl/mm/amd64/init.cc
@@ -0,0 +1,25 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/mm/amd64/init.cc
+ * DESCRIPTION:     Architecture specific Memory Manager initialization routines
+ * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/**
+ * Performs architecture specific initialization of the XTOS Memory Manager.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::Init::InitializeArchitecture(VOID)
+{
+    UNIMPLEMENTED;
+}
--- a/xtoskrnl/mm/amd64/pagemap.cc
+++ b/xtoskrnl/mm/amd64/pagemap.cc
@@ -1,12 +1,12 @@
 /**
 * PROJECT:         ExectOS
 * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/mm/amd64/pmap.c
- * DESCRIPTION:     Low-level support for AMD64 page map manipulation
+ * FILE:            xtoskrnl/mm/i686/pagemap.cc
+ * DESCRIPTION:     Low-level support for i686 page map manipulation
 * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
 */

-#include <xtos.h>
+#include <xtos.hh>


 /**
@@ -21,7 +21,7 @@
 */
 XTAPI
 VOID
-MmpClearPte(PHARDWARE_PTE PtePointer)
+MM::PageMap::ClearPte(PHARDWARE_PTE PtePointer)
 {
    PtePointer->CacheDisable = 0;
    PtePointer->PageFrameNumber = 0;
@@ -30,21 +30,6 @@ MmpClearPte(PHARDWARE_PTE PtePointer)
    PtePointer->WriteThrough = 0;
 }

-/**
- * Checks if eXtended Physical Addressing (XPA) is enabled.
- *
- * @return This routine returns TRUE if LA57 is enabled, or FALSE otherwise.
- *
- * @since XT 1.0
- */
-XTAPI
-BOOLEAN
-MmpGetExtendedPhysicalAddressingStatus(VOID)
-{
-    /* Check if LA57 is enabled */
-    return ((ArReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
-}
-
 /**
 * Gets the address of the P5E (Page Map Level 5 Entry), that maps given address.
 *
@@ -57,12 +42,13 @@ MmpGetExtendedPhysicalAddressingStatus(VOID)
 */
 XTAPI
 PMMP5E
-MmpGetP5eAddress(PVOID Address)
+MM::PageMap::GetP5eAddress(PVOID Address)
 {
    ULONGLONG Offset;

-    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << MmpPageMapInfo.VaBits) - 1)) >> MM_P5I_SHIFT) << MM_PTE_SHIFT);
-    return (PMMP5E)((MmpPageMapInfo.P5eBase + Offset) * MmpPageMapInfo.Xpa);
+    /* Calculate offset and return P5E address */
+    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << PageMapInfo.VaBits) - 1)) >> MM_P5I_SHIFT) << MM_PTE_SHIFT);
+    return (PMMP5E)((PageMapInfo.P5eBase + Offset) * PageMapInfo.Xpa);
 }

 /**
@@ -77,19 +63,20 @@ MmpGetP5eAddress(PVOID Address)
 */
 XTAPI
 PMMPDE
-MmpGetPdeAddress(PVOID Address)
+MM::PageMap::GetPdeAddress(PVOID Address)
 {
    ULONGLONG Offset;

-    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << MmpPageMapInfo.VaBits) - 1)) >> MM_PDI_SHIFT) << MM_PTE_SHIFT);
-    return (PMMPDE)(MmpPageMapInfo.PdeBase + Offset);
+    /* Calculate offset and return PDE address */
+    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << PageMapInfo.VaBits) - 1)) >> MM_PDI_SHIFT) << MM_PTE_SHIFT);
+    return (PMMPDE)(PageMapInfo.PdeBase + Offset);
 }

 /**
 * Gets the address of the PPE (Page Directory Pointer Table Entry), that maps given address.
 *
 * @param Address
- *        Specifies the virtual address for which to retrieve the corresponding PPE.
+ *        Specifies the virtual address for which to retrieve the corresponding PDE.
 *
 * @return This routine returns the address of the PPE.
 *
@@ -97,12 +84,13 @@ MmpGetPdeAddress(PVOID Address)
 */
 XTAPI
 PMMPPE
-MmpGetPpeAddress(PVOID Address)
+MM::PageMap::GetPpeAddress(PVOID Address)
 {
    ULONGLONG Offset;

-    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << MmpPageMapInfo.VaBits) - 1)) >> MM_PPI_SHIFT) << MM_PTE_SHIFT);
-    return (PMMPPE)(MmpPageMapInfo.PpeBase + Offset);
+    /* Calculate offset and return PPE address */
+    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << PageMapInfo.VaBits) - 1)) >> MM_PPI_SHIFT) << MM_PTE_SHIFT);
+    return (PMMPPE)(PageMapInfo.PpeBase + Offset);
 }

 /**
@@ -117,12 +105,13 @@ MmpGetPpeAddress(PVOID Address)
 */
 XTAPI
 PMMPTE
-MmpGetPteAddress(PVOID Address)
+MM::PageMap::GetPteAddress(PVOID Address)
 {
    ULONGLONG Offset;

-    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << MmpPageMapInfo.VaBits) - 1)) >> MM_PTI_SHIFT) << MM_PTE_SHIFT);
-    return (PMMPTE)(MmpPageMapInfo.PteBase + Offset);
+    /* Calculate offset and return PTE address */
+    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << PageMapInfo.VaBits) - 1)) >> MM_PTI_SHIFT) << MM_PTE_SHIFT);
+    return (PMMPTE)(PageMapInfo.PteBase + Offset);
 }

 /**
@@ -137,16 +126,16 @@ MmpGetPteAddress(PVOID Address)
 */
 XTAPI
 PMMPXE
-MmpGetPxeAddress(PVOID Address)
+MM::PageMap::GetPxeAddress(PVOID Address)
 {
    ULONGLONG Offset;

-    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << MmpPageMapInfo.VaBits) - 1)) >> MM_PXI_SHIFT) << MM_PTE_SHIFT);
-    return (PMMPXE)(MmpPageMapInfo.PxeBase + Offset);
+    Offset = ((((ULONGLONG)Address & (((ULONGLONG)1 << PageMapInfo.VaBits) - 1)) >> MM_PXI_SHIFT) << MM_PTE_SHIFT);
+    return (PMMPXE)(PageMapInfo.PxeBase + Offset);
 }

 /**
- * Checks whether the given page table entry (PTE) is valid.
+ * Checks whether the given PML2 page table entry (PTE) is valid.
 *
 * @param PtePointer
 *        Pointer to the page table entry (PTE) to check.
@@ -157,13 +146,13 @@ MmpGetPxeAddress(PVOID Address)
 */
 XTAPI
 BOOLEAN
-MmpPteValid(PHARDWARE_PTE PtePointer)
+MM::PageMap::PteValid(PHARDWARE_PTE PtePointer)
 {
    return (BOOLEAN)PtePointer->Valid;
 }

 /**
- * Sets a page table entry (PTE) with the specified physical page and access flags.
+ * Sets a PML2 page table entry (PTE) with the specified physical page and access flags.
 *
 * @param PtePointer
 *        Pointer to the page table entry (PTE) to set.
@@ -180,9 +169,9 @@ MmpPteValid(PHARDWARE_PTE PtePointer)
 */
 XTAPI
 VOID
-MmpSetPte(PHARDWARE_PTE PtePointer,
-          PFN_NUMBER PageFrameNumber,
-          BOOLEAN Writable)
+MM::PageMap::SetPte(PHARDWARE_PTE PtePointer,
+                    PFN_NUMBER PageFrameNumber,
+                    BOOLEAN Writable)
 {
    PtePointer->PageFrameNumber = PageFrameNumber;
    PtePointer->Valid = 1;
@@ -190,7 +179,7 @@ MmpSetPte(PHARDWARE_PTE PtePointer,
 }

 /**
- * Sets caching attributes for a page table entry (PTE).
+ * Sets caching attributes for a PML2 page table entry (PTE).
 *
 * @param PtePointer
 *        Pointer to the page table entry (PTE) to modify.
@@ -207,10 +196,60 @@ MmpSetPte(PHARDWARE_PTE PtePointer,
 */
 XTAPI
 VOID
-MmpSetPteCaching(PHARDWARE_PTE PtePointer,
-                 BOOLEAN CacheDisable,
-                 BOOLEAN WriteThrough)
+MM::PageMap::SetPteCaching(PHARDWARE_PTE PtePointer,
+                           BOOLEAN CacheDisable,
+                           BOOLEAN WriteThrough)
 {
    PtePointer->CacheDisable = CacheDisable;
    PtePointer->WriteThrough = WriteThrough;
 }
+
+/**
+ * Initializes page map information for basic paging (PML4).
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMapBasic::InitializePageMapInfo(VOID)
+{
+    /* Set PML4 page map information */
+    PageMapInfo.Xpa = FALSE;
+
+    /* Set PML4 base addresses */
+    PageMapInfo.PteBase = MM_PTE_BASE;
+    PageMapInfo.PdeBase = MM_PDE_BASE;
+    PageMapInfo.PpeBase = MM_PPE_BASE;
+    PageMapInfo.PxeBase = MM_PXE_BASE;
+    PageMapInfo.P5eBase = 0x0;
+
+    /* PML use 48-bit virtual addresses */
+    PageMapInfo.VaBits = 48;
+}
+
+/**
+ * Initializes page map information for XPA paging (PML5).
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MM::PageMapXpa::InitializePageMapInfo(VOID)
+{
+    /* Set PML5 page map information */
+    PageMapInfo.Xpa = TRUE;
+
+    /* Set PML5 base addresses */
+    PageMapInfo.PteBase = MM_PTE_LA57_BASE;
+    PageMapInfo.PdeBase = MM_PDE_LA57_BASE;
+    PageMapInfo.PpeBase = MM_PPE_LA57_BASE;
+    PageMapInfo.PxeBase = MM_PXE_LA57_BASE;
+    PageMapInfo.P5eBase = MM_P5E_LA57_BASE;
+
+    /* PML5 use 57-bit virtual addresses */
+    PageMapInfo.VaBits = 57;
+}
--- a/xtoskrnl/mm/amd64/paging.cc
+++ b/xtoskrnl/mm/amd64/paging.cc
@@ -1,14 +1,30 @@
 /**
 * PROJECT:         ExectOS
 * COPYRIGHT:       See COPYING.md in the top level directory
- * FILE:            xtoskrnl/mm/amd64/pages.c
+ * FILE:            xtoskrnl/mm/amd64/paging.cc
 * DESCRIPTION:     Architecture dependent paging support
 * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
+ *                  Aiken Harris <harraiken91@gmail.com>
 */

-#include <xtos.h>
+#include <xtos.hh>


+/**
+ * Checks if eXtended Physical Addressing (XPA) is enabled.
+ *
+ * @return This routine returns TRUE if LA57 is enabled, or FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MM::Paging::GetExtendedPhysicalAddressingStatus(VOID)
+{
+    /* Check if LA57 is enabled */
+    return ((AR::CpuFunc::ReadControlRegister(4) & CR4_LA57) != 0) ? TRUE : FALSE;
+}
+
 /**
 * Fills a section of memory with zeroes like RtlZeroMemory(), but in more efficient way.
 *
@@ -24,8 +40,8 @@
 */
 XTFASTCALL
 VOID
-MmZeroPages(IN PVOID Address,
-            IN ULONG Size)
+MM::Paging::ZeroPages(IN PVOID Address,
+                      IN ULONG Size)
 {
    __asm__ volatile("xor %%rax, %%rax\n"
                     "mov %0, %%rdi\n"