Merge branch 'master' into memmgr
This commit is contained in:
@@ -9,6 +9,41 @@
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#include <xtos.hh>
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/**
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* Checks whether the APIC is supported by the processor.
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*
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* @return This routine returns TRUE if APIC is supported, or FALSE otherwise.
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*
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* @since XT 1.0
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*/
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XTAPI
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BOOLEAN
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HL::Pic::CheckApicSupport(VOID)
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{
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CPUID_REGISTERS CpuRegisters;
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/* Prepare CPUID registers */
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CpuRegisters.Leaf = CPUID_GET_STANDARD1_FEATURES;
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CpuRegisters.SubLeaf = 0;
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CpuRegisters.Eax = 0;
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CpuRegisters.Ebx = 0;
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CpuRegisters.Ecx = 0;
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CpuRegisters.Edx = 0;
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/* Get CPUID */
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AR::CpuFunc::CpuId(&CpuRegisters);
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/* Check APIC status from the CPUID results */
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if(!(CpuRegisters.Edx & CPUID_FEATURES_EDX_APIC))
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{
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/* APIC is not supported */
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return FALSE;
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}
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/* APIC is supported */
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return TRUE;
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}
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/**
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* Checks whether the x2APIC extension is supported by the processor.
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*
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@@ -124,6 +159,14 @@ HL::Pic::InitializeApic(VOID)
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APIC_LVT_REGISTER LvtRegister;
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ULONG CpuNumber;
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/* Check APIC support */
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if(!CheckApicSupport())
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{
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/* APIC is not supported, raise kernel panic */
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DebugPrint(L"FATAL ERROR: Local APIC not present.\n");
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KE::Crash::Panic(0x5D, CPUID_GET_STANDARD1_FEATURES, 0x0, 0x0, CPUID_FEATURES_EDX_APIC);
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}
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/* Determine APIC mode (xAPIC compatibility or x2APIC) */
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if(CheckX2ApicSupport())
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{
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@@ -31,6 +31,13 @@ namespace AR
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OUT PVOID *TrampolineCode,
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OUT PULONG_PTR TrampolineSize);
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STATIC XTAPI VOID InitializeProcessor(IN PVOID ProcessorStructures);
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STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
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IN USHORT Vector,
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IN PVOID Handler,
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IN USHORT Selector,
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IN USHORT Ist,
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IN USHORT Dpl,
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IN USHORT Type);
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private:
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STATIC XTAPI VOID IdentifyProcessor(VOID);
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@@ -62,13 +69,6 @@ namespace AR
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STATIC XTAPI VOID SetGdtEntryBase(IN PKGDTENTRY Gdt,
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IN USHORT Selector,
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IN ULONG_PTR Base);
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STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
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IN USHORT Vector,
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IN PVOID Handler,
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IN USHORT Selector,
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IN USHORT Ist,
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IN USHORT Dpl,
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IN USHORT Type);
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};
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}
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@@ -34,6 +34,13 @@ namespace AR
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OUT PVOID *TrampolineCode,
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OUT PULONG_PTR TrampolineSize);
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STATIC XTAPI VOID InitializeProcessor(IN PVOID ProcessorStructures);
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STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
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IN USHORT Vector,
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IN PVOID Handler,
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IN USHORT Selector,
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IN USHORT Ist,
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IN USHORT Dpl,
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IN USHORT Type);
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private:
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STATIC XTAPI VOID IdentifyProcessor(VOID);
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@@ -67,13 +74,6 @@ namespace AR
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STATIC XTAPI VOID SetGdtEntryBase(IN PKGDTENTRY Gdt,
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IN USHORT Selector,
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IN ULONG_PTR Base);
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STATIC XTAPI VOID SetIdtGate(IN PKIDTENTRY Idt,
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IN USHORT Vector,
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IN PVOID Handler,
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IN USHORT Selector,
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IN USHORT Ist,
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IN USHORT Dpl,
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IN USHORT Type);
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STATIC XTAPI VOID SetNonMaskableInterruptTssEntry(IN PKPROCESSOR_BLOCK ProcessorBlock,
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IN PVOID KernelFaultStack);
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@@ -32,6 +32,7 @@ namespace HL
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IN ULONGLONG Value);
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private:
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STATIC XTAPI BOOLEAN CheckApicSupport(VOID);
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STATIC XTAPI BOOLEAN CheckX2ApicSupport(VOID);
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STATIC XTCDECL VOID HandleApicSpuriousService(VOID);
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STATIC XTCDECL VOID HandlePicSpuriousService(VOID);
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@@ -33,7 +33,11 @@ KE::Irq::SetInterruptHandler(IN ULONG Vector,
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ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
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/* Update interrupt handler */
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ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF);
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ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF);
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ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetHigh = (ULONG_PTR)Handler >> 32;
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AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase,
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Vector,
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Handler,
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KGDT_R0_CODE,
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0,
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KIDT_ACCESS_RING0,
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AMD64_INTERRUPT_GATE);
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}
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@@ -33,6 +33,11 @@ KE::Irq::SetInterruptHandler(IN ULONG Vector,
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ProcessorBlock = KE::Processor::GetCurrentProcessorBlock();
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/* Update interrupt handler */
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ProcessorBlock->IdtBase[(UCHAR) Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF);
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ProcessorBlock->IdtBase[(UCHAR) Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16);
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AR::ProcSup::SetIdtGate(ProcessorBlock->IdtBase,
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Vector,
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Handler,
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KGDT_R0_CODE,
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0,
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KIDT_ACCESS_RING0,
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I686_INTERRUPT_GATE);
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}
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