diff --git a/xtoskrnl/includes/i686/mmi.h b/xtoskrnl/includes/i686/mmi.h
index 218361b..cc36a58 100644
--- a/xtoskrnl/includes/i686/mmi.h
+++ b/xtoskrnl/includes/i686/mmi.h
@@ -22,6 +22,10 @@ VOID
 MmZeroPages(IN PVOID Address,
             IN ULONG Size);
 
+XTAPI
+VOID
+MmpClearPte(PHARDWARE_PTE PtePointer);
+
 XTAPI
 BOOLEAN
 MmpGetExtendedPhysicalAddressingStatus(VOID);
@@ -42,4 +46,36 @@ XTAPI
 VOID
 MmpInitializeArchitecture(VOID);
 
+XTAPI
+BOOLEAN
+MmpPml2PteValid(PHARDWARE_PTE PtePointer);
+
+XTAPI
+VOID
+MmpSetPml2Pte(PHARDWARE_PTE PtePointer,
+              PFN_NUMBER PageFrameNumber,
+              BOOLEAN Writable);
+
+XTAPI
+VOID
+MmpSetPml2PteCaching(PHARDWARE_PTE PtePointer,
+                     BOOLEAN CacheDisable,
+                     BOOLEAN WriteThrough);
+
+XTAPI
+BOOLEAN
+MmpPml3PteValid(PHARDWARE_PTE PtePointer);
+
+XTAPI
+VOID
+MmpSetPml3Pte(PHARDWARE_PTE PtePointer,
+              PFN_NUMBER PageFrameNumber,
+              BOOLEAN Writable);
+
+XTAPI
+VOID
+MmpSetPml3PteCaching(PHARDWARE_PTE PtePointer,
+                     BOOLEAN CacheDisable,
+                     BOOLEAN WriteThrough);
+
 #endif /* __XTOSKRNL_I686_MMI_H */
diff --git a/xtoskrnl/mm/i686/pmap.c b/xtoskrnl/mm/i686/pmap.c
index fbe5229..1c1034b 100644
--- a/xtoskrnl/mm/i686/pmap.c
+++ b/xtoskrnl/mm/i686/pmap.c
@@ -9,6 +9,23 @@
 #include <xtos.h>
 
 
+/**
+ * Clears the contents of a page table entry (PTE).
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to be cleared.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MmpClearPte(PHARDWARE_PTE PtePointer)
+{
+    PtePointer->Long = 0;
+}
+
 /**
  * Checks if eXtended Physical Addressing (XPA) is enabled.
  *
@@ -83,3 +100,143 @@ MmpGetPteAddress(PVOID Address)
     Offset = ((((ULONG)(Address)) >> MM_PTI_SHIFT) << MmpPageMapInfo.PteShift);
     return (PMMPTE)(MM_PTE_BASE + Offset);
 }
+
+/**
+ * Checks whether the given PML2 page table entry (PTE) is valid.
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to check.
+ *
+ * @return Returns TRUE if the entry is valid, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MmpPml2PteValid(PHARDWARE_PTE PtePointer)
+{
+    return (BOOLEAN)PtePointer->Pml2.Valid;
+}
+
+/**
+ * Sets a PML2 page table entry (PTE) with the specified physical page and access flags.
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to set.
+ *
+ * @param PageFrameNumber
+ *        Physical frame number to map.
+ *
+ * @param Writable
+ *        Indicates whether the page should be writable.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MmpSetPml2Pte(PHARDWARE_PTE PtePointer,
+            PFN_NUMBER PageFrameNumber,
+            BOOLEAN Writable)
+{
+    PtePointer->Pml2.PageFrameNumber = PageFrameNumber;
+    PtePointer->Pml2.Valid = 1;
+    PtePointer->Pml2.Writable = Writable;
+}
+
+/**
+ * Sets caching attributes for a PML2 page table entry (PTE).
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to modify.
+ *
+ * @param CacheDisable
+ *        Indicates whether caching should be disabled for this page.
+ *
+ * @param WriteThrough
+ *        Indicates whether write-through caching should be enabled.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MmpSetPml2PteCaching(PHARDWARE_PTE PtePointer,
+                    BOOLEAN CacheDisable,
+                    BOOLEAN WriteThrough)
+{
+    PtePointer->Pml2.CacheDisable = CacheDisable;
+    PtePointer->Pml2.WriteThrough = WriteThrough;
+}
+
+/**
+ * Checks whether the given PML3 page table entry (PTE) is valid.
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to check.
+ *
+ * @return Returns TRUE if the entry is valid, FALSE otherwise.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+BOOLEAN
+MmpPml3PteValid(PHARDWARE_PTE PtePointer)
+{
+    return PtePointer->Pml3.Valid;
+}
+
+/**
+ * Sets a PML3 page table entry (PTE) with the specified physical page and access flags.
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to set.
+ *
+ * @param PageFrameNumber
+ *        Physical frame number to map.
+ *
+ * @param Writable
+ *        Indicates whether the page should be writable.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MmpSetPml3Pte(PHARDWARE_PTE PtePointer,
+            PFN_NUMBER PageFrameNumber,
+            BOOLEAN Writable)
+{
+    PtePointer->Pml3.PageFrameNumber = PageFrameNumber;
+    PtePointer->Pml3.Valid = 1;
+    PtePointer->Pml3.Writable = Writable;
+}
+
+/**
+ * Sets caching attributes for a PML3 page table entry (PTE).
+ *
+ * @param PtePointer
+ *        Pointer to the page table entry (PTE) to modify.
+ *
+ * @param CacheDisable
+ *        Indicates whether caching should be disabled for this page.
+ *
+ * @param WriteThrough
+ *        Indicates whether write-through caching should be enabled.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+MmpSetPml3PteCaching(PHARDWARE_PTE PtePointer,
+                    BOOLEAN CacheDisable,
+                    BOOLEAN WriteThrough)
+{
+    PtePointer->Pml3.CacheDisable = CacheDisable;
+    PtePointer->Pml3.WriteThrough = WriteThrough;
+}