Implement CMOS register access functions

sdk/xtdk/amd64/hltypes.h

@@ -54,6 +54,10 @@
 /* Maximum number of I/O APICs */
 #define APIC_MAX_IOAPICS                                64
 
+/* CMOS controller I/O ports */
+#define CMOS_ADDRESS_PORT                               0x70
+#define CMOS_DATA_PORT                                  0x71
+
 /* I/O APIC base address */
 #define IOAPIC_DEFAULT_BASE                             0xFEC00000
 
@@ -87,6 +91,8 @@
 /* PIT ports definitions */
 #define PIT_COMMAND_PORT                                0x43
 #define PIT_DATA_PORT0                                  0x40
+#define PIT_DATA_PORT1                                  0x41
+#define PIT_DATA_PORT2                                  0x42
 
 /* Serial ports information */
 #define COMPORT_ADDRESS                                 {0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8}

sdk/xtdk/i686/hltypes.h

@@ -37,6 +37,7 @@
 #define APIC_VECTOR_GENERIC                             0xC1
 #define APIC_VECTOR_SYNC                                0xC1
 #define APIC_VECTOR_CLOCK                               0xD1
+#define APIC_VECTOR_CLOCK_IPI                           0xD2
 #define APIC_VECTOR_IPI                                 0xE1
 #define APIC_VECTOR_ERROR                               0xE3
 #define APIC_VECTOR_POWERFAIL                           0xEF
@@ -59,6 +60,10 @@
 /* Maximum number of I/O APICs */
 #define APIC_MAX_IOAPICS                                64
 
+/* CMOS controller I/O ports */
+#define CMOS_ADDRESS_PORT                               0x70
+#define CMOS_DATA_PORT                                  0x71
+
 /* I/O APIC base address */
 #define IOAPIC_DEFAULT_BASE                             0xFEC00000
 

xtoskrnl/CMakeLists.txt

@@ -17,9 +17,10 @@ list(APPEND XTOSKRNL_SOURCE
     ${XTOSKRNL_SOURCE_DIR}/ex/exports.cc
     ${XTOSKRNL_SOURCE_DIR}/ex/rundown.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/cpu.cc
-    ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/pic.cc
+    ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/firmware.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/ioport.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/irq.cc
+    ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/pic.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/runlevel.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/${ARCH}/timer.cc
     ${XTOSKRNL_SOURCE_DIR}/hl/acpi.cc

xtoskrnl/hl/amd64/firmware.cc

@@ -0,0 +1,13 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/amd64/firmware.cc
+ * DESCRIPTION:     UEFI/BIOS Firmware support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/* Include common Firmware interface */
+#include ARCH_COMMON(firmware.cc)

xtoskrnl/hl/i686/firmware.cc

@@ -0,0 +1,13 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/i686/firmware.cc
+ * DESCRIPTION:     UEFI/BIOS Firmware support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/* Include common Firmware interface */
+#include ARCH_COMMON(firmware.cc)

xtoskrnl/hl/x86/firmware.cc

@@ -0,0 +1,56 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/hl/x86/firmware.cc
+ * DESCRIPTION:     UEFI/BIOS Firmware support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#include <xtos.hh>
+
+
+/**
+ * Reads a byte from the specified CMOS register.
+ *
+ * @param Register
+ *        Supplies the CMOS register index to read from.
+ *
+ * @return This routine returns the data read from the register.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+UCHAR
+HL::Firmware::ReadCmosRegister(IN UCHAR Register)
+{
+    /* Select the register (Setting the highest bit disables NMI) */
+    HL::IoPort::WritePort8(CMOS_ADDRESS_PORT, Register | 0x80);
+
+    /* Read value from the data port */
+    return HL::IoPort::ReadPort8(CMOS_DATA_PORT);
+}
+
+/**
+ * Writes a byte to the specified CMOS register.
+ *
+ * @param Register
+ *        Supplies the CMOS register index to write to.
+ *
+ * @param Value
+ *        Supplies the value to write to the register.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTFASTCALL
+VOID
+HL::Firmware::WriteCmosRegister(IN UCHAR Register,
+                                IN UCHAR Value)
+{
+    /* Select the register (Setting the highest bit disables NMI) */
+    HL::IoPort::WritePort8(CMOS_ADDRESS_PORT, Register | 0x80);
+
+    /* Write the provided value to the data port */
+    HL::IoPort::WritePort8(CMOS_DATA_PORT, Value);
+}

xtoskrnl/includes/hl.hh

@@ -15,6 +15,7 @@
 #include <hl/cport.hh>
 #include <hl/cpu.hh>
 #include <hl/fbdev.hh>
+#include <hl/firmware.hh>
 #include <hl/init.hh>
 #include <hl/ioport.hh>
 #include <hl/ioreg.hh>

xtoskrnl/includes/hl/firmware.hh

@@ -0,0 +1,27 @@
+/**
+ * PROJECT:         ExectOS
+ * COPYRIGHT:       See COPYING.md in the top level directory
+ * FILE:            xtoskrnl/includes/hl/firmware.hh
+ * DESCRIPTION:     UEFI/BIOS Firmware support
+ * DEVELOPERS:      Aiken Harris <harraiken91@gmail.com>
+ */
+
+#ifndef __XTOSKRNL_HL_FIRMWARE_HH
+#define __XTOSKRNL_HL_FIRMWARE_HH
+
+#include <xtos.hh>
+
+
+/* Hardware Layer */
+namespace HL
+{
+    class Firmware
+    {
+        public:
+            STATIC XTFASTCALL UCHAR ReadCmosRegister(IN UCHAR Register);
+            STATIC XTFASTCALL VOID WriteCmosRegister(IN UCHAR Register,
+                                                     IN UCHAR Value);
+    };
+}
+
+#endif /* __XTOSKRNL_HL_FIRMWARE_HH */