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Refactor memory layout structure
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This commit is contained in:
Aiken Harris
2026-01-29 22:10:26 +01:00
parent 72f34c8286
commit 58669d3074
10 changed files with 67 additions and 47 deletions
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12
xtoskrnl/mm/amd64/mmgr.cc
View File

@@ -39,11 +39,11 @@ MM::Manager::InitializeMemoryLayout(VOID)
if(MM::Paging::GetXpaStatus())
{
/* Configure memory layout for 5-level paging, using 57bit address space and providing a 128 PB address space */
MemoryLayout.PfnDatabaseAddress = (PMMPFN)0xFFFEFA8000000000ULL;
MemoryLayout.PfnDatabase = (PMMPFN)0xFFFEFA8000000000ULL;
MemoryLayout.SelfMapAddress = (PVOID)MM_P5E_LA57_BASE;
/* Define the non-paged and paged pool regions */
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabaseAddress + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabase + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolEnd = (PVOID)0xFFFEFFFFFFBFFFFFULL;
MemoryLayout.PagedPoolStart = (PVOID)0xFFFEF8A000000000ULL;
MemoryLayout.PagedPoolEnd = (PVOID)(((ULONG_PTR)MemoryLayout.PagedPoolStart + PagedPoolSize) - 1);
@@ -51,18 +51,16 @@ MM::Manager::InitializeMemoryLayout(VOID)
/* Define hyperspace, system PTE space, and the user space limit */
MemoryLayout.HyperSpaceStart = (PVOID)0xFFFEF70000000000ULL;
MemoryLayout.HyperSpaceEnd = (PVOID)0xFFFEF77FFFFFFFFFULL;
MemoryLayout.SystemSpaceStart = (PVOID)0xFFFEF88000000000ULL;
MemoryLayout.SystemSpaceEnd = (PVOID)((ULONG_PTR)MemoryLayout.SystemSpaceStart + (NumberOfSystemPtes + 1) * MM_PAGE_SIZE);
MemoryLayout.UserSpaceEnd = (PVOID)0x07FFFFFFFFFFFFFULL;
}
else
{
/* Configure memory layout for 4-level paging, using 48bit address space and providing a 128 TB address space */
MemoryLayout.PfnDatabaseAddress = (PMMPFN)0xFFFFFA8000000000ULL;
MemoryLayout.PfnDatabase = (PMMPFN)0xFFFFFA8000000000ULL;
MemoryLayout.SelfMapAddress = (PVOID)MM_PXE_BASE;
/* Define the non-paged and paged pool regions */
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabaseAddress + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolStart = (PVOID)((ULONG_PTR)MemoryLayout.PfnDatabase + PfnDatabaseSize * MM_PAGE_SIZE);
MemoryLayout.NonPagedPoolEnd = (PVOID)0xFFFFFFFFFFBFFFFFULL;
MemoryLayout.PagedPoolStart = (PVOID)0xFFFFF8A000000000ULL;
MemoryLayout.PagedPoolEnd = (PVOID)(((ULONG_PTR)MemoryLayout.PagedPoolStart + PagedPoolSize) - 1);
@@ -70,8 +68,6 @@ MM::Manager::InitializeMemoryLayout(VOID)
/* Define hyperspace, system PTE space, and the user space limit */
MemoryLayout.HyperSpaceStart = (PVOID)0xFFFFF70000000000ULL;
MemoryLayout.HyperSpaceEnd = (PVOID)0xFFFFF77FFFFFFFFFULL;
MemoryLayout.SystemSpaceStart = (PVOID)0xFFFFF88000000000ULL;
MemoryLayout.SystemSpaceEnd = (PVOID)((ULONG_PTR)MemoryLayout.SystemSpaceStart + (NumberOfSystemPtes + 1) * MM_PAGE_SIZE);
MemoryLayout.UserSpaceEnd = (PVOID)0x000007FFFFFEFFFFULL;
}
}

10
xtoskrnl/mm/amd64/pfn.cc
View File

@@ -40,14 +40,14 @@ MM::Pfn::InitializePfnDatabase(VOID)
MemoryLayout = MM::Manager::GetMemoryLayout();
/* Get the PFN database size and calculate the end of the PFN database virtual address space */
PfnDatabaseEnd = (PUCHAR)MemoryLayout->PfnDatabaseAddress + (PfnDatabaseSize * MM_PAGE_SIZE) - 1;
PfnDatabaseEnd = (PUCHAR)MemoryLayout->PfnDatabase + (PfnDatabaseSize * MM_PAGE_SIZE) - 1;
/* Get a template PTE for mapping the PFN database pages */
ValidPte = MM::Pte::GetValidPte();
/* Map the Page Directory and Page Directory Pointer tables for the PFN database */
MM::Pte::MapPPE(MemoryLayout->PfnDatabaseAddress, PfnDatabaseEnd, ValidPte);
MM::Pte::MapPDE(MemoryLayout->PfnDatabaseAddress, PfnDatabaseEnd, ValidPte);
MM::Pte::MapPPE(MemoryLayout->PfnDatabase, PfnDatabaseEnd, ValidPte);
MM::Pte::MapPDE(MemoryLayout->PfnDatabase, PfnDatabaseEnd, ValidPte);
/* Initialize the color tables */
MM::Colors::InitializeColorTables();
@@ -80,8 +80,8 @@ MM::Pfn::InitializePfnDatabase(VOID)
}
/* Map PFN database entries for this physical range */
MM::Pte::MapPTE(&((PMMPFN)MemoryLayout->PfnDatabaseAddress)[BasePage],
(PUCHAR)&((PMMPFN)MemoryLayout->PfnDatabaseAddress)[BasePage + PageCount] - 1,
MM::Pte::MapPTE(&((PMMPFN)MemoryLayout->PfnDatabase)[BasePage],
(PUCHAR)&((PMMPFN)MemoryLayout->PfnDatabase)[BasePage + PageCount] - 1,
ValidPte);
/* Split PFN database allocation out of the free descriptor */

2
xtoskrnl/mm/amd64/pte.cc
View File

@@ -68,7 +68,7 @@ MM::Pte::GetSystemPteBaseAddress(VOID)
if(MM::Paging::GetXpaStatus())
{
/* For 5-level paging, system PTEs start at the beginning of system space */
return MM::Paging::GetPteAddress((PVOID)MemoryLayout->SystemSpaceStart);
return MM::Paging::GetPteAddress((PVOID)MemoryLayout->NonPagedSystemPoolStart);
}
else
{