From 0e6844e2fa8ae091d6cb5f6b3ab967ae5adfe83b Mon Sep 17 00:00:00 2001 From: Rafal Kupiec Date: Sun, 26 Nov 2023 14:14:54 +0100 Subject: [PATCH 1/7] Fix page fault on accessing initial thread frame --- xtoskrnl/ke/i686/kthread.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xtoskrnl/ke/i686/kthread.c b/xtoskrnl/ke/i686/kthread.c index 77bd8d5..c7109c1 100644 --- a/xtoskrnl/ke/i686/kthread.c +++ b/xtoskrnl/ke/i686/kthread.c @@ -43,7 +43,7 @@ KepInitializeThreadContext(IN PKTHREAD Thread, PFX_SAVE_FORMAT FxSaveFormat; /* Set initial thread frame */ - ThreadFrame = ((PKTHREAD_INIT_FRAME)Thread->InitialStack) - sizeof(KTHREAD_INIT_FRAME); + ThreadFrame = (PKTHREAD_INIT_FRAME)(Thread->InitialStack - sizeof(KTHREAD_INIT_FRAME)); /* Fill floating point save area with zeroes */ RtlZeroMemory(&ThreadFrame->NpxFrame, sizeof(FX_SAVE_AREA)); From 5b48525b1dcad36a468a19546924f7b7a61adc9c Mon Sep 17 00:00:00 2001 From: Rafal Kupiec Date: Sun, 26 Nov 2023 16:26:22 +0100 Subject: [PATCH 2/7] Increase commit hash to 10 characters to match Gitea --- sdk/cmake/version.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sdk/cmake/version.cmake b/sdk/cmake/version.cmake index 243067a..141814a 100644 --- a/sdk/cmake/version.cmake +++ b/sdk/cmake/version.cmake @@ -17,7 +17,7 @@ string(TIMESTAMP XTOS_VERSION_FULLDATE "%d/%m/%Y %H:%M UTC" UTC) # Set latest GIT revision set(XTOS_VERSION_HASH "unknown") if(EXISTS "${EXECTOS_SOURCE_DIR}/.git") - execute_process(COMMAND git describe --abbrev=7 --long --always + execute_process(COMMAND git describe --abbrev=10 --long --always WORKING_DIRECTORY ${EXECTOS_SOURCE_DIR} OUTPUT_VARIABLE XTOS_VERSION_HASH OUTPUT_STRIP_TRAILING_WHITESPACE) From e886baa0d867a70ce6fc7542551e5b882c890efa Mon Sep 17 00:00:00 2001 From: Rafal Kupiec Date: Sun, 26 Nov 2023 16:57:40 +0100 Subject: [PATCH 3/7] Fix reading from and writting to APIC registers --- xtoskrnl/hl/pic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/xtoskrnl/hl/pic.c b/xtoskrnl/hl/pic.c index c0d33ff..b2fc1cc 100644 --- a/xtoskrnl/hl/pic.c +++ b/xtoskrnl/hl/pic.c @@ -23,7 +23,7 @@ XTFASTCALL ULONG HlReadApicRegister(IN APIC_REGISTER Register) { - return RtlReadRegisterLong((PULONG)APIC_BASE + (Register << 4)); + return RtlReadRegisterLong((PULONG)(APIC_BASE + (Register << 4))); } /** @@ -44,5 +44,5 @@ VOID HlWriteApicRegister(IN APIC_REGISTER Register, IN ULONG Value) { - RtlWriteRegisterLong((PULONG)APIC_BASE + (Register << 4), Value); + RtlWriteRegisterLong((PULONG)(APIC_BASE + (Register << 4)), Value); } From 4ca4e298f0dbf51916129e823c65bd17ea0baa81 Mon Sep 17 00:00:00 2001 From: Rafal Kupiec Date: Sun, 26 Nov 2023 23:35:14 +0100 Subject: [PATCH 4/7] Add more PIC/APIC related definitions --- sdk/xtdk/amd64/hltypes.h | 32 +++++++++++++++++++++++++++++++- sdk/xtdk/i686/hltypes.h | 32 +++++++++++++++++++++++++++++++- 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/sdk/xtdk/amd64/hltypes.h b/sdk/xtdk/amd64/hltypes.h index 3fd7c4c..19d228d 100644 --- a/sdk/xtdk/amd64/hltypes.h +++ b/sdk/xtdk/amd64/hltypes.h @@ -15,8 +15,9 @@ #include ARCH_HEADER(xtstruct.h) -/* APIC base address */ +/* APIC base addresses */ #define APIC_BASE 0xFFFFFFFFFFFE0000 +#define APIC_MSR_BASE 0x0000001B /* APIC vector definitions */ #define APIC_VECTOR_ZERO 0x00 @@ -36,6 +37,35 @@ #define APIC_VECTOR_PERF 0xFE #define APIC_VECTOR_NMI 0xFF +/* APIC destination formats */ +#define APIC_DF_FLAT 0xFFFFFFFF +#define APIC_DF_CLUSTER 0x0FFFFFFF + +/* APIC delivery modes */ +#define APIC_DM_FIXED 0 +#define APIC_DM_LOWPRIO 1 +#define APIC_DM_SMI 2 +#define APIC_DM_REMOTE 3 +#define APIC_DM_NMI 4 +#define APIC_DM_INIT 5 +#define APIC_DM_STARTUP 6 +#define APIC_DM_EXTINT 7 + +/* APIC trigger modes */ +#define APIC_TGM_EDGE 0 +#define APIC_TGM_LEVEL 1 + +/* 8259/ISP PIC ports definitions */ +#define PIC1_CONTROL_PORT 0x20 +#define PIC1_DATA_PORT 0x21 +#define PIC1_ELCR_PORT 0x04D0 +#define PIC2_CONTROL_PORT 0xA0 +#define PIC2_DATA_PORT 0xA1 +#define PIC2_ELCR_PORT 0x04D1 + +/* PIC vector definitions */ +#define PIC1_VECTOR_SPURIOUS 0x37 + /* Serial port I/O addresses */ #define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8} diff --git a/sdk/xtdk/i686/hltypes.h b/sdk/xtdk/i686/hltypes.h index 90fdb7a..47628bd 100644 --- a/sdk/xtdk/i686/hltypes.h +++ b/sdk/xtdk/i686/hltypes.h @@ -15,8 +15,9 @@ #include ARCH_HEADER(xtstruct.h) -/* APIC base address */ +/* APIC base addresses */ #define APIC_BASE 0xFFFE0000 +#define APIC_MSR_BASE 0x0000001B /* APIC vector definitions */ #define APIC_VECTOR_ZERO 0x00 @@ -41,6 +42,35 @@ #define APIC_VECTOR_PERF 0xFE #define APIC_VECTOR_NMI 0xFF +/* APIC destination formats */ +#define APIC_DF_FLAT 0xFFFFFFFF +#define APIC_DF_CLUSTER 0x0FFFFFFF + +/* APIC delivery modes */ +#define APIC_DM_FIXED 0 +#define APIC_DM_LOWPRIO 1 +#define APIC_DM_SMI 2 +#define APIC_DM_REMOTE 3 +#define APIC_DM_NMI 4 +#define APIC_DM_INIT 5 +#define APIC_DM_STARTUP 6 +#define APIC_DM_EXTINT 7 + +/* APIC trigger modes */ +#define APIC_TGM_EDGE 0 +#define APIC_TGM_LEVEL 1 + +/* 8259/ISP PIC ports definitions */ +#define PIC1_CONTROL_PORT 0x20 +#define PIC1_DATA_PORT 0x21 +#define PIC1_ELCR_PORT 0x04D0 +#define PIC2_CONTROL_PORT 0xA0 +#define PIC2_DATA_PORT 0xA1 +#define PIC2_ELCR_PORT 0x04D1 + +/* PIC vector definitions */ +#define PIC1_VECTOR_SPURIOUS 0x37 + /* Serial port I/O addresses */ #define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8} From e5adc31af7033bc30000e51e13e4961f79df5714 Mon Sep 17 00:00:00 2001 From: Rafal Kupiec Date: Mon, 27 Nov 2023 22:38:15 +0100 Subject: [PATCH 5/7] Implement basic APIC support, including X2APIC --- sdk/xtdk/amd64/hltypes.h | 51 +++++++++- sdk/xtdk/hltypes.h | 11 ++- sdk/xtdk/i686/hltypes.h | 51 +++++++++- xtoskrnl/hl/globals.c | 3 + xtoskrnl/hl/pic.c | 180 +++++++++++++++++++++++++++++++++++- xtoskrnl/includes/globals.h | 3 + xtoskrnl/includes/hl.h | 16 ++++ 7 files changed, 307 insertions(+), 8 deletions(-) diff --git a/sdk/xtdk/amd64/hltypes.h b/sdk/xtdk/amd64/hltypes.h index 19d228d..ab06ce2 100644 --- a/sdk/xtdk/amd64/hltypes.h +++ b/sdk/xtdk/amd64/hltypes.h @@ -17,7 +17,8 @@ /* APIC base addresses */ #define APIC_BASE 0xFFFFFFFFFFFE0000 -#define APIC_MSR_BASE 0x0000001B +#define APIC_LAPIC_MSR_BASE 0x0000001B +#define APIC_X2APIC_MSR_BASE 0x00000800 /* APIC vector definitions */ #define APIC_VECTOR_ZERO 0x00 @@ -69,4 +70,52 @@ /* Serial port I/O addresses */ #define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8} +/* APIC Base Register */ +typedef union _APIC_BASE_REGISTER +{ + ULONGLONG LongLong; + struct + { + ULONGLONG Reserved1:8; + ULONGLONG BootStrapProcessor:1; + ULONGLONG Reserved2:1; + ULONGLONG ExtendedMode:1; + ULONGLONG Enable:1; + ULONGLONG BaseAddress:40; + ULONGLONG Reserved3:12; + }; +} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER; + +/* APIC Local Vector Table (LVT) Register */ +typedef union _APIC_LVT_REGISTER +{ + ULONG Long; + struct + { + ULONG Vector:8; + ULONG MessageType:3; + ULONG Reserved1:1; + ULONG DeliveryStatus:1; + ULONG Reserved2:1; + ULONG RemoteIRR:1; + ULONG TriggerMode:1; + ULONG Mask:1; + ULONG TimerMode:1; + ULONG Reserved3:13; + }; +} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER; + +/* APIC Spurious Register */ +typedef union _APIC_SPURIOUS_REGISTER +{ + ULONG Long; + struct + { + ULONG Vector:8; + ULONG SoftwareEnable:1; + ULONG CoreChecking:1; + ULONG Reserved:22; + }; +} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER; + #endif /* __XTDK_AMD64_HLTYPES_H */ diff --git a/sdk/xtdk/hltypes.h b/sdk/xtdk/hltypes.h index 8eec8f2..bfcee77 100644 --- a/sdk/xtdk/hltypes.h +++ b/sdk/xtdk/hltypes.h @@ -101,14 +101,14 @@ typedef enum _APIC_REGISTER APIC_EOI = 0x0B, /* EOI Register */ APIC_RRR = 0x0C, /* Remote Read Register */ APIC_LDR = 0x0D, /* Logical Destination Register */ - APIC_DFR = 0x0E, /* Destination Format Register */ + APIC_DFR = 0x0E, /* Destination Format Register (not available in extended mode) */ APIC_SIVR = 0x0F, /* Spurious Interrupt Vector Register */ APIC_ISR = 0x10, /* Interrupt Service Register*/ APIC_TMR = 0x18, /* Trigger Mode Register */ APIC_IRR = 0x20, /* Interrupt Request Register */ APIC_ESR = 0x28, /* Error Status Register */ APIC_ICR0 = 0x30, /* Interrupt Command Register */ - APIC_ICR1 = 0x31, /* Interrupt Command Register */ + APIC_ICR1 = 0x31, /* Interrupt Command Register (not available in extended mode) */ APIC_TMRLVTR = 0x32, /* Timer Local Vector Table */ APIC_THRMLVTR = 0x33, /* Thermal Local Vector Table */ APIC_PCLVTR = 0x34, /* Performance Counter Local Vector Table */ @@ -127,6 +127,13 @@ typedef enum _APIC_REGISTER APIC_EXT3LVTR = 0x53 /* Extended Interrupt 3 Local Vector Table */ } APIC_REGISTER, *PAPIC_REGISTER; +/* APIC mode list */ +typedef enum _HAL_APIC_MODE +{ + APIC_MODE_COMPAT, + APIC_MODE_X2APIC +} HAL_APIC_MODE, *PHAL_APIC_MODE; + /* Serial (COM) port initial state */ typedef struct _CPPORT { diff --git a/sdk/xtdk/i686/hltypes.h b/sdk/xtdk/i686/hltypes.h index 47628bd..386175c 100644 --- a/sdk/xtdk/i686/hltypes.h +++ b/sdk/xtdk/i686/hltypes.h @@ -17,7 +17,8 @@ /* APIC base addresses */ #define APIC_BASE 0xFFFE0000 -#define APIC_MSR_BASE 0x0000001B +#define APIC_LAPIC_MSR_BASE 0x0000001B +#define APIC_X2APIC_MSR_BASE 0x00000800 /* APIC vector definitions */ #define APIC_VECTOR_ZERO 0x00 @@ -74,4 +75,52 @@ /* Serial port I/O addresses */ #define COMPORT_ADDRESSES {0x000, 0x3F8, 0x2F8, 0x3E8, 0x2E8, 0x5F8, 0x4F8, 0x5E8, 0x4E8} +/* APIC Base Register */ +typedef union _APIC_BASE_REGISTER +{ + ULONGLONG LongLong; + struct + { + ULONGLONG Reserved1:8; + ULONGLONG BootStrapProcessor:1; + ULONGLONG Reserved2:1; + ULONGLONG ExtendedMode:1; + ULONGLONG Enable:1; + ULONGLONG BaseAddress:40; + ULONGLONG Reserved3:12; + }; +} APIC_BASE_REGISTER, *PAPIC_BASE_REGISTER; + +/* APIC Local Vector Table (LVT) Register */ +typedef union _APIC_LVT_REGISTER +{ + ULONG Long; + struct + { + ULONG Vector:8; + ULONG MessageType:3; + ULONG Reserved1:1; + ULONG DeliveryStatus:1; + ULONG Reserved2:1; + ULONG RemoteIRR:1; + ULONG TriggerMode:1; + ULONG Mask:1; + ULONG TimerMode:1; + ULONG Reserved3:13; + }; +} APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER; + +/* APIC Spurious Register */ +typedef union _APIC_SPURIOUS_REGISTER +{ + ULONG Long; + struct + { + ULONG Vector:8; + ULONG SoftwareEnable:1; + ULONG CoreChecking:1; + ULONG Reserved:22; + }; +} APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER; + #endif /* __XTDK_I686_HLTYPES_H */ diff --git a/xtoskrnl/hl/globals.c b/xtoskrnl/hl/globals.c index 15c38f9..8bf7ecb 100644 --- a/xtoskrnl/hl/globals.c +++ b/xtoskrnl/hl/globals.c @@ -9,5 +9,8 @@ #include +/* APIC mode */ +HAL_APIC_MODE HlpApicMode; + /* FrameBuffer information */ HAL_FRAMEBUFFER_DATA HlpFrameBufferData; diff --git a/xtoskrnl/hl/pic.c b/xtoskrnl/hl/pic.c index b2fc1cc..85b932f 100644 --- a/xtoskrnl/hl/pic.c +++ b/xtoskrnl/hl/pic.c @@ -10,7 +10,7 @@ /** - * Reads from the local APIC register. + * Reads from the APIC register. * * @param Register * Supplies the APIC register to read from. @@ -23,11 +23,20 @@ XTFASTCALL ULONG HlReadApicRegister(IN APIC_REGISTER Register) { - return RtlReadRegisterLong((PULONG)(APIC_BASE + (Register << 4))); + if(HlpApicMode == APIC_MODE_X2APIC) + { + /* Read from x2APIC MSR */ + return ArReadModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register)); + } + else + { + /* Read from xAPIC */ + return RtlReadRegisterLong((PULONG)(APIC_BASE + (Register << 4))); + } } /** - * Writes to the local APIC register. + * Writes to the APIC register. * * @param Register * Supplies the APIC register to write to. @@ -44,5 +53,168 @@ VOID HlWriteApicRegister(IN APIC_REGISTER Register, IN ULONG Value) { - RtlWriteRegisterLong((PULONG)(APIC_BASE + (Register << 4)), Value); + if(HlpApicMode == APIC_MODE_X2APIC) + { + /* Write to x2APIC MSR */ + ArWriteModelSpecificRegister((ULONG)(APIC_X2APIC_MSR_BASE + Register), Value); + } + else + { + /* Write to xAPIC */ + RtlWriteRegisterLong((PULONG)(APIC_BASE + (Register << 4)), Value); + } +} + +/** + * Checks whether the x2APIC extension is supported by the processor. + * + * @return This routine returns TRUE if x2APIC is supported, or FALSE otherwise. + * + * @since XT 1.0 + * + * @todo Check if bits 0 and 1 of DMAR ACPI table flags are set after implementing ACPI support. + * Intel VT-d spec says x2apic should not be enabled if they are. + */ +XTAPI +BOOLEAN +HlpCheckX2ApicSupport(VOID) +{ + CPUID_REGISTERS CpuRegisters; + + /* Prepare CPUID registers */ + CpuRegisters.Leaf = CPUID_GET_CPU_FEATURES; + CpuRegisters.SubLeaf = 0; + CpuRegisters.Eax = 0; + CpuRegisters.Ebx = 0; + CpuRegisters.Ecx = 0; + CpuRegisters.Edx = 0; + + /* Get CPUID */ + ArCpuId(&CpuRegisters); + + /* Check x2APIC status from the CPUID results */ + if(!(CpuRegisters.Ecx & CPUID_FEATURES_ECX_X2APIC)) + { + /* x2APIC is not supported */ + return FALSE; + } + + /* x2APIC is supported */ + return TRUE; +} + +/** + * Allows an APIC spurious interrupts to end up. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlpHandleApicSpuriousService() +{ +} + +/** + * Allows a PIC spurious interrupts to end up. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlpHandlePicSpuriousService() +{ +} + +/** + * Initializes the APIC interrupt controller. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + * + * @todo Register interrupt handlers for spurious vectors. + */ +XTAPI +VOID +HlpInitializeApic() +{ + APIC_BASE_REGISTER BaseRegister; + APIC_LVT_REGISTER LvtRegister; + APIC_SPURIOUS_REGISTER SpuriousRegister; + ULONG CpuNumber = 0; + + /* Check if this is an x2APIC compatible machine */ + if(HlpCheckX2ApicSupport()) + { + /* Enable x2APIC */ + HlpApicMode = APIC_MODE_X2APIC; + } + else + { + /* Use xAPIC compatibility mode */ + HlpApicMode = APIC_MODE_COMPAT; + } + + /* Enable the APIC */ + BaseRegister.LongLong = ArReadModelSpecificRegister(APIC_LAPIC_MSR_BASE); + BaseRegister.Enable = 1; + BaseRegister.ExtendedMode = (HlpApicMode == APIC_MODE_X2APIC); + BaseRegister.BootStrapProcessor = 1; + ArWriteModelSpecificRegister(APIC_LAPIC_MSR_BASE, BaseRegister.LongLong); + + /* xAPIC compatibility mode specific initialization */ + if(HlpApicMode == APIC_MODE_COMPAT) + { + /* Initialize Destination Format Register with flat model */ + HlWriteApicRegister(APIC_DFR, APIC_DF_FLAT); + + /* Set the logical APIC ID */ + HlWriteApicRegister(APIC_LDR, (1UL << CpuNumber) << 24); + } + + /* Set the spurious interrupt vector and register interrupt handlers */ + SpuriousRegister.Long = HlReadApicRegister(APIC_SIVR); + SpuriousRegister.Vector = APIC_VECTOR_SPURIOUS; + SpuriousRegister.SoftwareEnable = 1; + SpuriousRegister.CoreChecking = 0; + HlWriteApicRegister(APIC_SIVR, SpuriousRegister.Long); + + /* Initialize Logical Vector Table */ + LvtRegister.Long = 0; + LvtRegister.Vector = APIC_VECTOR_NMI; + LvtRegister.MessageType = APIC_DM_FIXED; + LvtRegister.DeliveryStatus = 0; + LvtRegister.RemoteIRR = 0; + LvtRegister.TriggerMode = APIC_TGM_EDGE; + LvtRegister.Mask = 0; + LvtRegister.TimerMode = 0; + + /* Mask LVT tables */ + HlWriteApicRegister(APIC_TMRLVTR, LvtRegister.Long); + HlWriteApicRegister(APIC_THRMLVTR, LvtRegister.Long); + HlWriteApicRegister(APIC_PCLVTR, LvtRegister.Long); + + /* Mask LINT0 */ + LvtRegister.Vector = APIC_VECTOR_SPURIOUS; + LvtRegister.MessageType = APIC_DM_EXTINT; + HlWriteApicRegister(APIC_LINT0, LvtRegister.Long); + + /* Mask LINT1 */ + LvtRegister.Mask = 0; + LvtRegister.Vector = APIC_VECTOR_NMI; + LvtRegister.MessageType = APIC_DM_NMI; + LvtRegister.TriggerMode = APIC_TGM_LEVEL; + HlWriteApicRegister(APIC_LINT1, LvtRegister.Long); + + /* Mask LVTR_ERROR */ + LvtRegister.Vector = APIC_VECTOR_ERROR; + LvtRegister.MessageType = APIC_DM_FIXED; + HlWriteApicRegister(APIC_ERRLVTR, LvtRegister.Long); + + /* Clear errors after enabling vectors */ + HlWriteApicRegister(APIC_ESR, 0); } diff --git a/xtoskrnl/includes/globals.h b/xtoskrnl/includes/globals.h index 98a3671..70b111a 100644 --- a/xtoskrnl/includes/globals.h +++ b/xtoskrnl/includes/globals.h @@ -12,6 +12,9 @@ #include +/* APIC mode */ +EXTERN HAL_APIC_MODE HlpApicMode; + /* FrameBuffer information */ EXTERN HAL_FRAMEBUFFER_DATA HlpFrameBufferData; diff --git a/xtoskrnl/includes/hl.h b/xtoskrnl/includes/hl.h index 6ff39d1..215d208 100644 --- a/xtoskrnl/includes/hl.h +++ b/xtoskrnl/includes/hl.h @@ -69,6 +69,22 @@ VOID HlWriteApicRegister(IN APIC_REGISTER Register, IN ULONG Value); +XTAPI +BOOLEAN +HlpCheckX2ApicSupport(VOID); + +XTCDECL +VOID +HlpHandleApicSpuriousService(); + +XTCDECL +VOID +HlpHandlePicSpuriousService(); + +XTAPI +VOID +HlpInitializeApic(); + XTFASTCALL KRUNLEVEL HlpTransformApicTprToRunLevel(IN UCHAR Tpr); From c4ccf52782d1638739ad8456468f6233049b5aba Mon Sep 17 00:00:00 2001 From: Rafal Kupiec Date: Tue, 28 Nov 2023 14:05:08 +0100 Subject: [PATCH 6/7] Correct code formatting --- sdk/cmake/qemu.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sdk/cmake/qemu.cmake b/sdk/cmake/qemu.cmake index c70f67b..806233f 100644 --- a/sdk/cmake/qemu.cmake +++ b/sdk/cmake/qemu.cmake @@ -8,14 +8,14 @@ endif() # This target creates a disk image add_custom_target(diskimg DEPENDS install - COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null" + COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_DISK_IMAGE_BLOCKS} 2>/dev/null 1>/dev/null" COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mklabel gpt COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal mkpart EFI FAT32 2048s ${PROJECT_PART_IMAGE_BLOCKS}s COMMAND parted ${EXECTOS_BINARY_DIR}/output/disk.img -s -a minimal toggle 1 boot - COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} 2> /dev/null 1> /dev/null" + COMMAND sh -c "dd if=/dev/zero of=${EXECTOS_BINARY_DIR}/output/part.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} 2>/dev/null 1>/dev/null" COMMAND mformat -i ${EXECTOS_BINARY_DIR}/output/part.img -h32 -t32 -n64 -L32 COMMAND sh -c "mcopy -s -i ${EXECTOS_BINARY_DIR}/output/part.img ${EXECTOS_BINARY_DIR}/output/binaries/* ::" - COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc 2> /dev/null 1> /dev/null" + COMMAND sh -c "dd if=${EXECTOS_BINARY_DIR}/output/part.img of=${EXECTOS_BINARY_DIR}/output/disk.img bs=512 count=${PROJECT_PART_IMAGE_BLOCKS} seek=2048 conv=notrunc 2>/dev/null 1>/dev/null" COMMAND rm ${EXECTOS_BINARY_DIR}/output/part.img VERBATIM) From d17b06a180d4c4cf12fa2364dc31c4ae5858f735 Mon Sep 17 00:00:00 2001 From: Rafal Kupiec Date: Tue, 28 Nov 2023 14:20:23 +0100 Subject: [PATCH 7/7] Register interrupt handlers once the APIC initialization is done --- xtoskrnl/CMakeLists.txt | 1 + xtoskrnl/ar/amd64/procsup.c | 4 ++-- xtoskrnl/hl/pic.c | 6 +++++- xtoskrnl/includes/ke.h | 5 +++++ xtoskrnl/ke/amd64/irqs.c | 39 +++++++++++++++++++++++++++++++++++++ xtoskrnl/ke/i686/irqs.c | 38 ++++++++++++++++++++++++++++++++++++ 6 files changed, 90 insertions(+), 3 deletions(-) create mode 100644 xtoskrnl/ke/amd64/irqs.c create mode 100644 xtoskrnl/ke/i686/irqs.c diff --git a/xtoskrnl/CMakeLists.txt b/xtoskrnl/CMakeLists.txt index f24a455..175a3e6 100644 --- a/xtoskrnl/CMakeLists.txt +++ b/xtoskrnl/CMakeLists.txt @@ -31,6 +31,7 @@ list(APPEND XTOSKRNL_SOURCE ${XTOSKRNL_SOURCE_DIR}/ke/semphore.c ${XTOSKRNL_SOURCE_DIR}/ke/spinlock.c ${XTOSKRNL_SOURCE_DIR}/ke/timer.c + ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/irqs.c ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/krnlinit.c ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/kthread.c ${XTOSKRNL_SOURCE_DIR}/ke/${ARCH}/proc.c diff --git a/xtoskrnl/ar/amd64/procsup.c b/xtoskrnl/ar/amd64/procsup.c index 417368e..778d1d9 100644 --- a/xtoskrnl/ar/amd64/procsup.c +++ b/xtoskrnl/ar/amd64/procsup.c @@ -539,8 +539,8 @@ ArpSetIdtGate(IN PKIDTENTRY Idt, IN USHORT Access) { /* Setup the gate */ - Idt[Vector].OffsetLow = (ULONG_PTR)Handler; - Idt[Vector].OffsetMiddle = ((ULONG_PTR)Handler >> 16); + Idt[Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF); + Idt[Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF); Idt[Vector].OffsetHigh = (ULONG_PTR)Handler >> 32; Idt[Vector].Dpl = Access; Idt[Vector].IstIndex = Ist; diff --git a/xtoskrnl/hl/pic.c b/xtoskrnl/hl/pic.c index 85b932f..e1c5b09 100644 --- a/xtoskrnl/hl/pic.c +++ b/xtoskrnl/hl/pic.c @@ -176,7 +176,7 @@ HlpInitializeApic() HlWriteApicRegister(APIC_LDR, (1UL << CpuNumber) << 24); } - /* Set the spurious interrupt vector and register interrupt handlers */ + /* Set the spurious interrupt vector */ SpuriousRegister.Long = HlReadApicRegister(APIC_SIVR); SpuriousRegister.Vector = APIC_VECTOR_SPURIOUS; SpuriousRegister.SoftwareEnable = 1; @@ -217,4 +217,8 @@ HlpInitializeApic() /* Clear errors after enabling vectors */ HlWriteApicRegister(APIC_ESR, 0); + + /* Register interrupt handlers once the APIC initialization is done */ + KeSetInterruptHandler(APIC_VECTOR_SPURIOUS, HlpHandleApicSpuriousService); + KeSetInterruptHandler(PIC1_VECTOR_SPURIOUS, HlpHandlePicSpuriousService); } diff --git a/xtoskrnl/includes/ke.h b/xtoskrnl/includes/ke.h index 39fab33..0b49d99 100644 --- a/xtoskrnl/includes/ke.h +++ b/xtoskrnl/includes/ke.h @@ -77,6 +77,11 @@ KeSetEvent(IN PKEVENT Event, IN KPRIORITY Increment, IN BOOLEAN Wait); +XTAPI +VOID +KeSetInterruptHandler(IN ULONG Vector, + IN PVOID Handler); + XTAPI VOID KeStartThread(IN PKTHREAD Thread); diff --git a/xtoskrnl/ke/amd64/irqs.c b/xtoskrnl/ke/amd64/irqs.c new file mode 100644 index 0000000..8fbf992 --- /dev/null +++ b/xtoskrnl/ke/amd64/irqs.c @@ -0,0 +1,39 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/ke/amd64/irqs.c + * DESCRIPTION: Kernel interrupts support for amd64 architecture + * DEVELOPERS: Rafal Kupiec + */ + +#include + + +/** + * Sets new interrupt handler for the existing IDT entry. + * + * @param HalVector + * Supplies the HAL vector number. + * + * @param Handler + * Supplies the new interrupt handler. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +KeSetInterruptHandler(IN ULONG Vector, + IN PVOID Handler) +{ + PKPROCESSOR_BLOCK ProcessorBlock; + + /* Get current processor block */ + ProcessorBlock = KeGetCurrentProcessorBlock(); + + /* Update interrupt handler */ + ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetLow = ((ULONG_PTR)Handler & 0xFFFF); + ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetMiddle = (((ULONG_PTR)Handler >> 16) & 0xFFFF); + ProcessorBlock->IdtBase[(UCHAR) Vector].OffsetHigh = (ULONG_PTR)Handler >> 32; +} diff --git a/xtoskrnl/ke/i686/irqs.c b/xtoskrnl/ke/i686/irqs.c new file mode 100644 index 0000000..20aa214 --- /dev/null +++ b/xtoskrnl/ke/i686/irqs.c @@ -0,0 +1,38 @@ +/** + * PROJECT: ExectOS + * COPYRIGHT: See COPYING.md in the top level directory + * FILE: xtoskrnl/ke/i686/irqs.c + * DESCRIPTION: Kernel interrupts support for i686 architecture + * DEVELOPERS: Rafal Kupiec + */ + +#include + + +/** + * Sets new interrupt handler for the existing IDT entry. + * + * @param HalVector + * Supplies the HAL vector number. + * + * @param Handler + * Supplies the new interrupt handler. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTAPI +VOID +KeSetInterruptHandler(IN ULONG Vector, + IN PVOID Handler) +{ + PKPROCESSOR_BLOCK ProcessorBlock; + + /* Get current processor block */ + ProcessorBlock = KeGetCurrentProcessorBlock(); + + /* Update interrupt handler */ + ProcessorBlock->IdtBase[(UCHAR) Vector].Offset = (USHORT)((ULONG)Handler & 0xFFFF); + ProcessorBlock->IdtBase[(UCHAR) Vector].ExtendedOffset = (USHORT)((ULONG)Handler >> 16); +}