diff --git a/xtoskrnl/ar/i686/procsup.c b/xtoskrnl/ar/i686/procsup.c
index 0d1e5e0..e3e8731 100644
--- a/xtoskrnl/ar/i686/procsup.c
+++ b/xtoskrnl/ar/i686/procsup.c
@@ -58,9 +58,15 @@ ArInitializeProcessor(VOID)
     /* Enter passive IRQ level */
     ProcessorBlock->Irql = PASSIVE_LEVEL;
 
+    /* Initialize segment registers */
+    ArpInitializeSegments();
+
     /* Load FS segment */
     ArLoadSegment(SEGMENT_FS, KGDT_R0_PB);
 
+    /* Initialize processor registers */
+    ArpInitializeProcessorRegisters();
+
     /* Identify processor */
     ArpIdentifyProcessor();
 }
@@ -209,6 +215,39 @@ ArpInitializeProcessorBlock(OUT PKPROCESSOR_BLOCK ProcessorBlock,
     ProcessorBlock->Prcb.ProcessorState.SpecialRegisters.KernelDr7 = 0;
 }
 
+/**
+ * Initializes processor registers and other boot structures.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+ArpInitializeProcessorRegisters(VOID)
+{
+    /* Clear EFLAGS register */
+    ArWriteEflagsRegister(0);
+
+    /* Enable write-protection */
+    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
+}
+
+/**
+ * Initializes segment registers.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+ArpInitializeSegments(VOID)
+{
+    ArLoadSegment(SEGMENT_DS, KGDT_R3_DATA | RPL_MASK);
+    ArLoadSegment(SEGMENT_ES, KGDT_R3_DATA | RPL_MASK);
+}
+
 /**
  * Initializes the kernel's Task State Segment (TSS).
  *
diff --git a/xtoskrnl/ke/i686/krnlinit.c b/xtoskrnl/ke/i686/krnlinit.c
index af5d5c0..9d841d8 100644
--- a/xtoskrnl/ke/i686/krnlinit.c
+++ b/xtoskrnl/ke/i686/krnlinit.c
@@ -20,12 +20,6 @@ XTAPI
 VOID
 KepArchInitialize(VOID)
 {
-    /* Clear EFLAGS register */
-    ArWriteEflagsRegister(0);
-
-    /* Enable write-protection */
-    ArWriteControlRegister(0, ArReadControlRegister(0) | CR0_WP);
-
     /* Re-enable IDE interrupts */
     HlIoPortOutByte(0x376, 0);
     HlIoPortOutByte(0x3F6, 0);