feat: Add CPU vendor and features identification

Add functionality to identify the CPU vendor and features using the CPUID instruction.
The CPU vendor information is stored in the Processor Control Block (PRCB),
including the vendor name and a corresponding enumeration.
CPU features are also retrieved and stored in the PRCB.
Previously, the CPU vendor was not properly stored in the PRCB, caused by a missing type cast.
Using Rtl functions to copy the CPU vendor name to the PRCB.

Details:
- Introduced functions `ArpSetCpuVendor` and `ArpSetCpuFeatures` to set CPU vendor and features, respectively.
- Modified `ArpIdentifyProcessor` to call the new functions for vendor and features identification.
- Added `CPU_FEATURES` structure to `KPROCESSOR_CONTROL_BLOCK` structure to store CPU features.

Tests:
- Tested x86_64 on QEMU. Verified that the CPU vendor and features are correctly identified and stored in the PRCB.
This commit is contained in:
2023-11-23 23:22:54 +01:00
parent a01ccff6dc
commit a270c08dcf
8 changed files with 337 additions and 45 deletions

View File

@@ -61,11 +61,16 @@
#define SEGMENT_FS 0x64
#define SEGMENT_GS 0x65
/* CPUID vendor names */
#define CPUID_VENDOR_NAME_AMD "AuthenticAMD"
#define CPUID_VENDOR_NAME_INTEL "GenuineIntel"
/* CPU vendor enumeration list */
typedef enum _CPU_VENDOR
{
CPU_VENDOR_AMD = 0x68747541,
CPU_VENDOR_INTEL = 0x756e6547,
CPU_VENDOR_INVALID,
CPU_VENDOR_AMD,
CPU_VENDOR_INTEL,
CPU_VENDOR_UNKNOWN = 0xFFFFFFFF
} CPU_VENDOR, *PCPU_VENDOR;
@@ -95,7 +100,7 @@ typedef enum _CPUID_FEATURES
CPUID_FEATURES_ECX_X2APIC = 1 << 21,
CPUID_FEATURES_ECX_MOVBE = 1 << 22,
CPUID_FEATURES_ECX_POPCNT = 1 << 23,
CPUID_FEATURES_ECX_TSC = 1 << 24,
CPUID_FEATURES_ECX_TSC_DEADLINE = 1 << 24,
CPUID_FEATURES_ECX_AES = 1 << 25,
CPUID_FEATURES_ECX_XSAVE = 1 << 26,
CPUID_FEATURES_ECX_OSXSAVE = 1 << 27,
@@ -135,6 +140,79 @@ typedef enum _CPUID_FEATURES
CPUID_FEATURES_EDX_PBE = 1 << 31
} CPUID_FEATURES, *PCPUID_FEATURES;
/* CPU features, as reported by CPUID instruction */
typedef struct _CPU_FEATURES {
union {
struct {
BOOLEAN SSE3 : 1;
BOOLEAN PCLMUL : 1;
BOOLEAN DTES64 : 1;
BOOLEAN MONITOR : 1;
BOOLEAN DS_CPL : 1;
BOOLEAN VMX : 1;
BOOLEAN SMX : 1;
BOOLEAN EST : 1;
BOOLEAN TM2 : 1;
BOOLEAN SSSE3 : 1;
BOOLEAN CID : 1;
BOOLEAN SDBG : 1;
BOOLEAN FMA : 1;
BOOLEAN CX16 : 1;
BOOLEAN XTPR : 1;
BOOLEAN PDCM : 1;
BOOLEAN Reserved1 : 1; // Bit 16 is reserved
BOOLEAN PCID : 1;
BOOLEAN DCA : 1;
BOOLEAN SSE4_1 : 1;
BOOLEAN SSE4_2 : 1;
BOOLEAN X2APIC : 1;
BOOLEAN MOVBE : 1;
BOOLEAN POPCNT : 1;
BOOLEAN TSC_DEADLINE : 1;
BOOLEAN AES : 1;
BOOLEAN XSAVE : 1;
BOOLEAN OSXSAVE : 1;
BOOLEAN AVX : 1;
BOOLEAN F16C : 1;
BOOLEAN RDRAND : 1;
BOOLEAN HYPERVISOR : 1;
BOOLEAN FPU : 1;
BOOLEAN VME : 1;
BOOLEAN DE : 1;
BOOLEAN PSE : 1;
BOOLEAN TSC : 1;
BOOLEAN MSR : 1;
BOOLEAN PAE : 1;
BOOLEAN MCE : 1;
BOOLEAN CX8 : 1;
BOOLEAN APIC : 1;
BOOLEAN Reserved2 : 1; // Bit 10 is reserved
BOOLEAN SEP : 1;
BOOLEAN MTRR : 1;
BOOLEAN PGE : 1;
BOOLEAN MCA : 1;
BOOLEAN CMOV : 1;
BOOLEAN PAT : 1;
BOOLEAN PSE36 : 1;
BOOLEAN PSN : 1;
BOOLEAN CLFLUSH : 1;
BOOLEAN Reserved3 : 1; // Bit 20 is reserved
BOOLEAN DS : 1;
BOOLEAN ACPI : 1;
BOOLEAN MMX : 1;
BOOLEAN FXSR : 1;
BOOLEAN SSE : 1;
BOOLEAN SSE2 : 1;
BOOLEAN SS : 1;
BOOLEAN HTT : 1;
BOOLEAN TM : 1;
BOOLEAN Reserved4 : 1; // Bit 30 is reserved
BOOLEAN PBE : 1;
};
UINT64 AsUINT64;
};
} CPU_FEATURES, *PCPU_FEATURES;
/* CPUID requests */
typedef enum _CPUID_REQUESTS
{

View File

@@ -454,6 +454,7 @@ typedef struct _KPROCESSOR_CONTROL_BLOCK
UCHAR Number;
ULONG_PTR SetMember;
CPU_IDENTIFICATION CpuId;
CPU_FEATURES CpuFeatures;
KPROCESSOR_STATE ProcessorState;
ULONG_PTR MultiThreadProcessorSet;
KDPC_DATA DpcData[2];