From b639bf30779b8f9cf9b51b297752e5474f91fdf8 Mon Sep 17 00:00:00 2001 From: Aiken Harris Date: Mon, 18 Aug 2025 11:59:05 +0200 Subject: [PATCH] Implement PML5 self-mapping --- xtldr/arch/amd64/memory.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/xtldr/arch/amd64/memory.c b/xtldr/arch/amd64/memory.c index 9133174..9b4f58b 100644 --- a/xtldr/arch/amd64/memory.c +++ b/xtldr/arch/amd64/memory.c @@ -338,22 +338,21 @@ BlpSelfMapPml(IN PXTBL_PAGE_MAPPING PageMap, /* Check page map level */ if(PageMap->PageMapLevel == 5) { - /* Self-mapping for PML5 is not supported */ - BlDebugPrint(L"PML5 self-mapping not supported yet!\n"); - return STATUS_EFI_UNSUPPORTED; + /* Calculate PML index based on provided self map address for PML5 */ + PmlIndex = (SelfMapAddress >> MM_P5I_SHIFT) & 0x1FF; } else { - /* Calculate PML index based on provided self map address */ + /* Calculate PML index based on provided self map address for PML4 */ PmlIndex = (SelfMapAddress >> MM_PXI_SHIFT) & 0x1FF; - - /* Add self-mapping for PML4 */ - RtlZeroMemory(&PmlBase[PmlIndex], sizeof(HARDWARE_PTE)); - PmlBase[PmlIndex].PageFrameNumber = (UINT_PTR)PageMap->PtePointer / EFI_PAGE_SIZE; - PmlBase[PmlIndex].Valid = 1; - PmlBase[PmlIndex].Writable = 1; } + /* Add self-mapping */ + RtlZeroMemory(&PmlBase[PmlIndex], sizeof(HARDWARE_PTE)); + PmlBase[PmlIndex].PageFrameNumber = (UINT_PTR)PageMap->PtePointer / EFI_PAGE_SIZE; + PmlBase[PmlIndex].Valid = 1; + PmlBase[PmlIndex].Writable = 1; + /* Return success */ return STATUS_EFI_SUCCESS; }