Initialize MXCSR register

sdk/xtdk/amd64/arfuncs.h

@@ -44,6 +44,10 @@ XTCDECL
 VOID
 ArLoadInterruptDescriptorTable(IN PVOID Source);
 
+XTCDECL
+VOID
+ArLoadMxcsrRegister(IN ULONG Source);
+
 XTCDECL
 VOID
 ArLoadSegment(IN USHORT Segment,

xtoskrnl/ar/amd64/cpufunc.c

@@ -141,6 +141,25 @@ ArLoadInterruptDescriptorTable(IN PVOID Source)
                  : "memory");
 }
 
+/**
+ * Loads the value in the source operand into the MXCSR register
+ *
+ * @param Source
+ *        Supplies a source value to be loaded into the MXCSR register.
+ *
+ * @return This routine does not return any value.
+ *
+ * @since XT 1.0
+ */
+XTCDECL
+VOID
+ArLoadMxcsrRegister(IN ULONG Source)
+{
+    asm volatile("ldmxcsr %0"
+                 :
+                 : "m" (Source));
+}
+
 /**
  * Loads source data into specified segment.
  *

xtoskrnl/ar/amd64/procsup.c

@@ -66,6 +66,9 @@ ArInitializeProcessor(VOID)
 
     /* Initialize processor registers */
     ArpInitializeProcessorRegisters();
+
+    /* Identify processor */
+    ArpIdentifyProcessor();
 }
 
 /**
@@ -254,6 +257,9 @@ ArpInitializeProcessorRegisters(VOID)
     PatAttributes = (PAT_TYPE_WB << 0) | (PAT_TYPE_USWC << 8) | (PAT_TYPE_WEAK_UC << 16) | (PAT_TYPE_STRONG_UC << 24) |
                     (PAT_TYPE_WB << 32) | (PAT_TYPE_USWC << 40) | (PAT_TYPE_WEAK_UC << 48) | (PAT_TYPE_STRONG_UC << 56);
     ArWriteModelSpecificRegister(X86_MSR_PAT, PatAttributes);
+
+    /* Initialize MXCSR register */
+    ArLoadMxcsrRegister(INITIAL_MXCSR);
 }
 
 /**