Implement more CPU-related routines
This commit is contained in:
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f0c20074c6
commit
ccd0514416
GPG Key ID:
4E829243E0CFE6B4
@ -314,6 +314,75 @@ ArReadControlRegister(IN USHORT ControlRegister)
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return Value;
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}
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/**
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* Reads the specified CPU debug register and returns its value.
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*
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* @param DebugRegister
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* Supplies a number of a debug register to read from.
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*
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* @return The value stored in the specified debug register.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONG_PTR
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ArReadDebugRegister(IN USHORT DebugRegister)
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{
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ULONG_PTR Value;
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/* Read a value from specified DR register */
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switch(DebugRegister)
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{
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case 0:
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/* Read value from DR0 */
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asm volatile("mov %%dr0, %0"
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: "=r" (Value));
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break;
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case 1:
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/* Read value from DR1 */
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asm volatile("mov %%dr1, %0"
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: "=r" (Value));
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break;
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case 2:
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/* Read value from DR2 */
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asm volatile("mov %%dr2, %0"
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: "=r" (Value));
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break;
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case 3:
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/* Read value from DR3 */
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asm volatile("mov %%dr3, %0"
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: "=r" (Value));
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break;
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case 4:
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/* Read value from DR4 */
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asm volatile("mov %%dr4, %0"
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: "=r" (Value));
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break;
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case 5:
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/* Read value from DR5 */
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asm volatile("mov %%dr5, %0"
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: "=r" (Value));
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break;
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case 6:
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/* Read value from DR6 */
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asm volatile("mov %%dr6, %0"
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: "=r" (Value));
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break;
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case 7:
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/* Read value from DR7 */
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asm volatile("mov %%dr7, %0"
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: "=r" (Value));
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break;
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default:
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/* Invalid debug register set */
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Value = 0;
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break;
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}
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/* Return value read from given DR register */
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return Value;
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}
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/**
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* Reads quadword from a memory location specified by an offset relative to the beginning of the GS segment.
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*
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@ -361,6 +430,20 @@ ArReadModelSpecificRegister(IN ULONG Register)
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return ((ULONGLONG)High << 32) | Low;
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}
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/**
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* Reads the contents of the MXCSR control/status register.
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*
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* @return This routine returns the contents of the MXCSR register as a 32-bit unsigned integer value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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UINT
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ArReadMxCsrRegister()
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{
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return __builtin_ia32_stmxcsr();
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}
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/**
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* Reads the current value of the CPU's time-stamp counter.
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*
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@ -410,8 +493,8 @@ VOID
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ArStoreGlobalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sgdt %0"
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: "=m" (*(PSHORT)Destination)
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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@ -430,8 +513,28 @@ VOID
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ArStoreInterruptDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sidt %0"
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: "=m" (*(PSHORT)Destination)
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:
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: "memory");
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}
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/**
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* Stores LDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where LDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArStoreLocalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sldt %0"
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: "=m" (*(PSHORT)Destination)
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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@ -500,8 +603,8 @@ VOID
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ArStoreTaskRegister(OUT PVOID Destination)
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{
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asm volatile("str %0"
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: "=m" (*(PULONG)Destination)
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:
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: "m" (*(PULONG)Destination)
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: "memory");
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}
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@ -564,6 +667,78 @@ ArWriteControlRegister(IN USHORT ControlRegister,
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}
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}
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/**
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* Writes a value to the specified CPU debug register.
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*
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* @param DebugRegister
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* Supplies a number of a debug register for write operation.
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*
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* @param Value
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* Suplies a value to write to the specified DR register.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArWriteDebugRegister(IN USHORT DebugRegister,
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IN UINT_PTR Value)
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{
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/* Write a value into specified debug register */
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switch(DebugRegister)
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{
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case 0:
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/* Write value to DR0 */
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asm volatile("mov %0, %%dr0"
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:
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: "r" (Value)
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: "memory");
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case 1:
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/* Write value to DR1 */
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asm volatile("mov %0, %%dr1"
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:
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: "r" (Value)
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: "memory");
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case 2:
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/* Write value to DR2 */
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asm volatile("mov %0, %%dr2"
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:
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: "r" (Value)
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: "memory");
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case 3:
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/* Write value to DR3 */
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asm volatile("mov %0, %%dr3"
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:
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: "r" (Value)
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: "memory");
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case 4:
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/* Write value to DR4 */
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asm volatile("mov %0, %%dr4"
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:
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: "r" (Value)
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: "memory");
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case 5:
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/* Write value to DR5 */
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asm volatile("mov %0, %%dr5"
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:
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: "r" (Value)
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: "memory");
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case 6:
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/* Write value to DR6 */
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asm volatile("mov %0, %%dr6"
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:
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: "r" (Value)
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: "memory");
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case 7:
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/* Write value to DR7 */
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asm volatile("mov %0, %%dr7"
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:
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: "r" (Value)
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: "memory");
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}
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}
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/**
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* Writes the specified value to the program status and control (EFLAGS) register.
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*
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@ -289,6 +289,75 @@ ArReadControlRegister(IN USHORT ControlRegister)
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return Value;
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}
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/**
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* Reads the specified CPU debug register and returns its value.
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*
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* @param DebugRegister
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* Supplies a number of a debug register to read from.
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*
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* @return The value stored in the specified debug register.
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*
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* @since XT 1.0
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*/
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XTCDECL
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ULONG_PTR
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ArReadDebugRegister(IN USHORT DebugRegister)
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{
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ULONG_PTR Value;
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/* Read a value from specified DR register */
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switch(DebugRegister)
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{
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case 0:
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/* Read value from DR0 */
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asm volatile("mov %%dr0, %0"
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: "=r" (Value));
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break;
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case 1:
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/* Read value from DR1 */
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asm volatile("mov %%dr1, %0"
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: "=r" (Value));
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break;
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case 2:
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/* Read value from DR2 */
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asm volatile("mov %%dr2, %0"
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: "=r" (Value));
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break;
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case 3:
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/* Read value from DR3 */
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asm volatile("mov %%dr3, %0"
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: "=r" (Value));
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break;
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case 4:
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/* Read value from DR4 */
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asm volatile("mov %%dr4, %0"
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: "=r" (Value));
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break;
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case 5:
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/* Read value from DR5 */
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asm volatile("mov %%dr5, %0"
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: "=r" (Value));
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break;
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case 6:
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/* Read value from DR6 */
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asm volatile("mov %%dr6, %0"
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: "=r" (Value));
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break;
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case 7:
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/* Read value from DR7 */
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asm volatile("mov %%dr7, %0"
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: "=r" (Value));
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break;
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default:
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/* Invalid debug register set */
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Value = 0;
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break;
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}
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/* Return value read from given DR register */
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return Value;
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}
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/**
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* Reads dualword from a memory location specified by an offset relative to the beginning of the FS segment.
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*
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@ -332,6 +401,20 @@ ArReadModelSpecificRegister(IN ULONG Register)
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return Value;
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}
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/**
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* Reads the contents of the MXCSR control/status register.
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*
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* @return This routine returns the contents of the MXCSR register as a 32-bit unsigned integer value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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UINT
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ArReadMxCsrRegister()
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{
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return __builtin_ia32_stmxcsr();
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}
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/**
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* Reads the current value of the CPU's time-stamp counter.
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*
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@ -380,8 +463,8 @@ VOID
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ArStoreGlobalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sgdt %0"
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: "=m" (*(PSHORT)Destination)
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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@ -400,8 +483,28 @@ VOID
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ArStoreInterruptDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sidt %0"
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: "=m" (*(PSHORT)Destination)
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:
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: "memory");
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}
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/**
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* Stores LDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where LDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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ArStoreLocalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sldt %0"
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: "=m" (*(PSHORT)Destination)
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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@ -470,8 +573,8 @@ VOID
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ArStoreTaskRegister(OUT PVOID Destination)
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{
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asm volatile("str %0"
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: "=m" (*(PULONG)Destination)
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:
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: "m" (*(PULONG)Destination)
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: "memory");
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}
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@ -527,6 +630,65 @@ ArWriteControlRegister(IN USHORT ControlRegister,
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}
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}
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XTCDECL
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VOID
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ArWriteDebugRegister(IN USHORT DebugRegister,
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IN UINT_PTR Value)
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{
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/* Write a value into specified debug register */
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switch(DebugRegister)
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{
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case 0:
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/* Write value to DR0 */
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asm volatile("mov %0, %%dr0"
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:
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: "r" (Value)
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: "memory");
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case 1:
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/* Write value to DR1 */
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asm volatile("mov %0, %%dr1"
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:
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: "r" (Value)
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: "memory");
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case 2:
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/* Write value to DR2 */
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asm volatile("mov %0, %%dr2"
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:
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: "r" (Value)
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: "memory");
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case 3:
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/* Write value to DR3 */
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asm volatile("mov %0, %%dr3"
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:
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: "r" (Value)
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: "memory");
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case 4:
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/* Write value to DR4 */
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asm volatile("mov %0, %%dr4"
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:
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: "r" (Value)
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: "memory");
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case 5:
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/* Write value to DR5 */
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asm volatile("mov %0, %%dr5"
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:
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: "r" (Value)
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: "memory");
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case 6:
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/* Write value to DR6 */
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asm volatile("mov %0, %%dr6"
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:
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: "r" (Value)
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: "memory");
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case 7:
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/* Write value to DR7 */
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asm volatile("mov %0, %%dr7"
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:
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: "r" (Value)
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: "memory");
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}
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}
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/**
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* Writes the specified value to the program status and control (EFLAGS) register.
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*
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@ -62,6 +62,10 @@ XTCDECL
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ULONG_PTR
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ArReadControlRegister(IN USHORT ControlRegister);
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XTCDECL
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ULONG_PTR
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ArReadDebugRegister(IN USHORT DebugRegister);
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XTCDECL
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ULONGLONG
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ArReadGSQuadWord(ULONG Offset);
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@ -70,6 +74,10 @@ XTCDECL
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ULONGLONG
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ArReadModelSpecificRegister(IN ULONG Register);
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XTCDECL
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UINT
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ArReadMxCsrRegister();
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XTCDECL
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ULONGLONG
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ArReadTimeStampCounter();
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@ -92,6 +100,10 @@ XTCDECL
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VOID
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ArStoreInterruptDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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ArStoreLocalDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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ArStoreSegment(IN USHORT Segment,
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@ -106,6 +118,11 @@ VOID
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ArWriteControlRegister(IN USHORT ControlRegister,
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IN UINT_PTR Value);
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XTCDECL
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VOID
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ArWriteDebugRegister(IN USHORT DebugRegister,
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IN UINT_PTR Value);
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XTCDECL
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VOID
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ArWriteEflagsRegister(IN UINT_PTR Value);
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@ -58,6 +58,10 @@ XTCDECL
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ULONG_PTR
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ArReadControlRegister(IN USHORT ControlRegister);
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XTCDECL
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ULONG_PTR
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ArReadDebugRegister(IN USHORT DebugRegister);
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XTCDECL
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ULONG
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ArReadFSDualWord(ULONG Offset);
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@ -66,6 +70,10 @@ XTCDECL
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ULONGLONG
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ArReadModelSpecificRegister(IN ULONG Register);
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XTCDECL
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UINT
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ArReadMxCsrRegister();
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XTCDECL
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ULONGLONG
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ArReadTimeStampCounter();
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@ -88,6 +96,10 @@ XTCDECL
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VOID
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ArStoreInterruptDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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ArStoreLocalDescriptorTable(OUT PVOID Destination);
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XTCDECL
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VOID
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ArStoreSegment(IN USHORT Segment,
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@ -102,6 +114,11 @@ VOID
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ArWriteControlRegister(IN USHORT ControlRegister,
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IN UINT_PTR Value);
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XTCDECL
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VOID
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ArWriteDebugRegister(IN USHORT DebugRegister,
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IN UINT_PTR Value);
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XTCDECL
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VOID
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ArWriteEflagsRegister(IN UINT_PTR Value);
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