Initialize legacy PIC and mask all interrupts

sdk/xtdk/amd64/hltypes.h

@@ -59,10 +59,8 @@
 /* 8259/ISP PIC ports definitions */
 #define PIC1_CONTROL_PORT                               0x20
 #define PIC1_DATA_PORT                                  0x21
-#define PIC1_ELCR_PORT                                  0x04D0
 #define PIC2_CONTROL_PORT                               0xA0
 #define PIC2_DATA_PORT                                  0xA1
-#define PIC2_ELCR_PORT                                  0x04D1
 
 /* PIC vector definitions */
 #define PIC1_VECTOR_SPURIOUS                            0x37
@@ -95,6 +93,50 @@ typedef enum _APIC_MT
     APIC_MT_ExtInt = 7,
 } APIC_MT, *PAPIC_MT;
 
+/* I8259 PIC interrupt mode enumeration list */
+typedef enum _PIC_I8259_ICW1_INTERRUPT_MODE
+{
+    EdgeTriggered,
+    LevelTriggered
+} PIC_I8259_ICW1_INTERRUPT_MODE, *PPIC_I8259_ICW1_INTERRUPT_MODE;
+
+/* I8259 PIC interval enumeration list */
+typedef enum _PIC_I8259_ICW1_INTERVAL
+{
+    Interval8,
+    Interval4
+} PIC_I8259_ICW1_INTERVAL, *PPIC_I8259_ICW1_INTERVAL;
+
+/* I8259 PIC operating mode enumeration list */
+typedef enum _PIC_I8259_ICW1_OPERATING_MODE
+{
+    Cascade,
+    Single
+} PIC_I8259_ICW1_OPERATING_MODE, *PPIC_I8259_ICW1_OPERATING_MODE;
+
+/* I8259 PIC buffered mode enumeration list */
+typedef enum _PIC_I8259_ICW4_BUFFERED_MODE
+{
+    NonBuffered,
+    NonBuffered2,
+    BufferedSlave,
+    BufferedMaster
+} PIC_I8259_ICW4_BUFFERED_MODE, *PPIC_I8259_ICW4_BUFFERED_MODE;
+
+/* I8259 PIC End Of Interrupt (EOI) mode enumeration list */
+typedef enum _PIC_I8259_ICW4_EOI_MODE
+{
+    NormalEoi,
+    AutomaticEoi
+} PIC_I8259_ICW4_EOI_MODE, *PPIC_I8259_ICW4_EOI_MODE;
+
+/* I8259 PIC system mode enumeration list */
+typedef enum _PIC_I8259_ICW4_SYSTEM_MODE
+{
+    Mcs8085Mode,
+    New8086Mode
+} PIC_I8259_ICW4_SYSTEM_MODE, *PPIC_I8259_ICW4_SYSTEM_MODE;
+
 /* APIC Base Register */
 typedef union _APIC_BASE_REGISTER
 {
@@ -168,6 +210,71 @@ typedef union _APIC_SPURIOUS_REGISTER
     };
 } APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
 
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW1
+{
+    struct
+    {
+        UCHAR NeedIcw4:1;
+        UCHAR OperatingMode:1;
+        UCHAR Interval:1;
+        UCHAR InterruptMode:1;
+        UCHAR Init:1;
+        UCHAR InterruptVectorAddress:3;
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW1, *PPIC_I8259_ICW1;
+
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW2
+{
+    struct
+    {
+        UCHAR Sbz:3;
+        UCHAR InterruptVector:5;
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW2, *PPIC_I8259_ICW2;
+
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW3
+{
+    union
+    {
+        struct
+        {
+            UCHAR SlaveIrq0:1;
+            UCHAR SlaveIrq1:1;
+            UCHAR SlaveIrq2:1;
+            UCHAR SlaveIrq3:1;
+            UCHAR SlaveIrq4:1;
+            UCHAR SlaveIrq5:1;
+            UCHAR SlaveIrq6:1;
+            UCHAR SlaveIrq7:1;
+        };
+        struct
+        {
+            UCHAR SlaveId:3;
+            UCHAR Reserved:5;
+        };
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW3, *PPIC_I8259_ICW3;
+
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW4
+{
+    struct
+    {
+        UCHAR SystemMode:1;
+        UCHAR EoiMode:1;
+        UCHAR BufferedMode:2;
+        UCHAR SpecialFullyNestedMode:1;
+        UCHAR Reserved:3;
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW4, *PPIC_I8259_ICW4;
+
 /* Processor identity structure */
 typedef struct _HAL_PROCESSOR_IDENTITY
 {

sdk/xtdk/amd64/xtstruct.h

@@ -19,6 +19,12 @@ typedef enum _CPU_VENDOR CPU_VENDOR, *PCPU_VENDOR;
 typedef enum _CPUID_FEATURES CPUID_FEATURES, *PCPUID_FEATURES;
 typedef enum _CPUID_REQUESTS CPUID_REQUESTS, *PCPUID_REQUESTS;
 typedef enum _PAGE_SIZE PAGE_SIZE, *PPAGE_SIZE;
+typedef enum _PIC_I8259_ICW1_INTERRUPT_MODE PIC_I8259_ICW1_INTERRUPT_MODE, *PPIC_I8259_ICW1_INTERRUPT_MODE;
+typedef enum _PIC_I8259_ICW1_INTERVAL PIC_I8259_ICW1_INTERVAL, *PPIC_I8259_ICW1_INTERVAL;
+typedef enum _PIC_I8259_ICW1_OPERATING_MODE PIC_I8259_ICW1_OPERATING_MODE, *PPIC_I8259_ICW1_OPERATING_MODE;
+typedef enum _PIC_I8259_ICW4_BUFFERED_MODE PIC_I8259_ICW4_BUFFERED_MODE, *PPIC_I8259_ICW4_BUFFERED_MODE;
+typedef enum _PIC_I8259_ICW4_EOI_MODE PIC_I8259_ICW4_EOI_MODE, *PPIC_I8259_ICW4_EOI_MODE;
+typedef enum _PIC_I8259_ICW4_SYSTEM_MODE PIC_I8259_ICW4_SYSTEM_MODE, *PPIC_I8259_ICW4_SYSTEM_MODE;
 
 /* Architecture-specific structures forward references */
 typedef struct _CONTEXT CONTEXT, *PCONTEXT;
@@ -60,5 +66,9 @@ typedef union _MMPTE MMPDE, *PMMPDE;
 typedef union _MMPTE MMPPE, *PMMPPE;
 typedef union _MMPTE MMPTE, *PMMPTE;
 typedef union _MMPTE MMPXE, *PMMPXE;
+typedef union _PIC_I8259_ICW1 PIC_I8259_ICW1, *PPIC_I8259_ICW1;
+typedef union _PIC_I8259_ICW2 PIC_I8259_ICW2, *PPIC_I8259_ICW2;
+typedef union _PIC_I8259_ICW3 PIC_I8259_ICW3, *PPIC_I8259_ICW3;
+typedef union _PIC_I8259_ICW4 PIC_I8259_ICW4, *PPIC_I8259_ICW4;
 
 #endif /* __XTDK_AMD64_XTSTRUCT_H */

sdk/xtdk/i686/hltypes.h

@@ -100,6 +100,50 @@ typedef enum _APIC_MT
     APIC_MT_ExtInt = 7,
 } APIC_MT, *PAPIC_MT;
 
+/* I8259 PIC interrupt mode enumeration list */
+typedef enum _PIC_I8259_ICW1_INTERRUPT_MODE
+{
+    EdgeTriggered,
+    LevelTriggered
+} PIC_I8259_ICW1_INTERRUPT_MODE, *PPIC_I8259_ICW1_INTERRUPT_MODE;
+
+/* I8259 PIC interval enumeration list */
+typedef enum _PIC_I8259_ICW1_INTERVAL
+{
+    Interval8,
+    Interval4
+} PIC_I8259_ICW1_INTERVAL, *PPIC_I8259_ICW1_INTERVAL;
+
+/* I8259 PIC operating mode enumeration list */
+typedef enum _PIC_I8259_ICW1_OPERATING_MODE
+{
+    Cascade,
+    Single
+} PIC_I8259_ICW1_OPERATING_MODE, *PPIC_I8259_ICW1_OPERATING_MODE;
+
+/* I8259 PIC buffered mode enumeration list */
+typedef enum _PIC_I8259_ICW4_BUFFERED_MODE
+{
+    NonBuffered,
+    NonBuffered2,
+    BufferedSlave,
+    BufferedMaster
+} PIC_I8259_ICW4_BUFFERED_MODE, *PPIC_I8259_ICW4_BUFFERED_MODE;
+
+/* I8259 PIC End Of Interrupt (EOI) mode enumeration list */
+typedef enum _PIC_I8259_ICW4_EOI_MODE
+{
+    NormalEoi,
+    AutomaticEoi
+} PIC_I8259_ICW4_EOI_MODE, *PPIC_I8259_ICW4_EOI_MODE;
+
+/* I8259 PIC system mode enumeration list */
+typedef enum _PIC_I8259_ICW4_SYSTEM_MODE
+{
+    Mcs8085Mode,
+    New8086Mode
+} PIC_I8259_ICW4_SYSTEM_MODE, *PPIC_I8259_ICW4_SYSTEM_MODE;
+
 /* APIC Base Register */
 typedef union _APIC_BASE_REGISTER
 {
@@ -173,6 +217,71 @@ typedef union _APIC_SPURIOUS_REGISTER
     };
 } APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
 
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW1
+{
+    struct
+    {
+        UCHAR NeedIcw4:1;
+        UCHAR OperatingMode:1;
+        UCHAR Interval:1;
+        UCHAR InterruptMode:1;
+        UCHAR Init:1;
+        UCHAR InterruptVectorAddress:3;
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW1, *PPIC_I8259_ICW1;
+
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW2
+{
+    struct
+    {
+        UCHAR Sbz:3;
+        UCHAR InterruptVector:5;
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW2, *PPIC_I8259_ICW2;
+
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW3
+{
+    union
+    {
+        struct
+        {
+            UCHAR SlaveIrq0:1;
+            UCHAR SlaveIrq1:1;
+            UCHAR SlaveIrq2:1;
+            UCHAR SlaveIrq3:1;
+            UCHAR SlaveIrq4:1;
+            UCHAR SlaveIrq5:1;
+            UCHAR SlaveIrq6:1;
+            UCHAR SlaveIrq7:1;
+        };
+        struct
+        {
+            UCHAR SlaveId:3;
+            UCHAR Reserved:5;
+        };
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW3, *PPIC_I8259_ICW3;
+
+/* I8259 PIC register structure */
+typedef union _PIC_I8259_ICW4
+{
+    struct
+    {
+        UCHAR SystemMode:1;
+        UCHAR EoiMode:1;
+        UCHAR BufferedMode:2;
+        UCHAR SpecialFullyNestedMode:1;
+        UCHAR Reserved:3;
+    };
+    UCHAR Bits;
+} PIC_I8259_ICW4, *PPIC_I8259_ICW4;
+
 /* Processor identity structure */
 typedef struct _HAL_PROCESSOR_IDENTITY
 {

sdk/xtdk/i686/xtstruct.h

@@ -19,6 +19,12 @@ typedef enum _CPU_VENDOR CPU_VENDOR, *PCPU_VENDOR;
 typedef enum _CPUID_FEATURES CPUID_FEATURES, *PCPUID_FEATURES;
 typedef enum _CPUID_REQUESTS CPUID_REQUESTS, *PCPUID_REQUESTS;
 typedef enum _PAGE_SIZE PAGE_SIZE, *PPAGE_SIZE;
+typedef enum _PIC_I8259_ICW1_INTERRUPT_MODE PIC_I8259_ICW1_INTERRUPT_MODE, *PPIC_I8259_ICW1_INTERRUPT_MODE;
+typedef enum _PIC_I8259_ICW1_INTERVAL PIC_I8259_ICW1_INTERVAL, *PPIC_I8259_ICW1_INTERVAL;
+typedef enum _PIC_I8259_ICW1_OPERATING_MODE PIC_I8259_ICW1_OPERATING_MODE, *PPIC_I8259_ICW1_OPERATING_MODE;
+typedef enum _PIC_I8259_ICW4_BUFFERED_MODE PIC_I8259_ICW4_BUFFERED_MODE, *PPIC_I8259_ICW4_BUFFERED_MODE;
+typedef enum _PIC_I8259_ICW4_EOI_MODE PIC_I8259_ICW4_EOI_MODE, *PPIC_I8259_ICW4_EOI_MODE;
+typedef enum _PIC_I8259_ICW4_SYSTEM_MODE PIC_I8259_ICW4_SYSTEM_MODE, *PPIC_I8259_ICW4_SYSTEM_MODE;
 
 /* Architecture-specific structures forward references */
 typedef struct _CONTEXT CONTEXT, *PCONTEXT;
@@ -61,5 +67,10 @@ typedef union _APIC_LVT_REGISTER APIC_LVT_REGISTER, *PAPIC_LVT_REGISTER;
 typedef union _APIC_SPURIOUS_REGISTER APIC_SPURIOUS_REGISTER, *PAPIC_SPURIOUS_REGISTER;
 typedef union _MMPTE MMPDE, *PMMPDE;
 typedef union _MMPTE MMPTE, *PMMPTE;
+typedef union _PIC_I8259_ICW1 PIC_I8259_ICW1, *PPIC_I8259_ICW1;
+typedef union _PIC_I8259_ICW2 PIC_I8259_ICW2, *PPIC_I8259_ICW2;
+typedef union _PIC_I8259_ICW3 PIC_I8259_ICW3, *PPIC_I8259_ICW3;
+typedef union _PIC_I8259_ICW4 PIC_I8259_ICW4, *PPIC_I8259_ICW4;
+
 
 #endif /* __XTDK_I686_XTSTRUCT_H */

xtoskrnl/hl/x86/pic.c

@@ -4,7 +4,6 @@
  * FILE:            xtoskrnl/hl/x86/pic.c
  * DESCRIPTION:     Programmable Interrupt Controller (PIC) for x86 (i686/AMD64) support
  * DEVELOPERS:      Rafal Kupiec <belliash@codingworkshop.eu.org>
- *                  Jozef Nagy <schkwve@gmail.com>
  */
 
 #include <xtos.h>
@@ -25,22 +24,6 @@ HlClearApicErrors(VOID)
     HlWriteApicRegister(APIC_ESR, 0);
 }
 
-/**
- * Disables the legacy 8259 Programmable Interrupt Controller (PIC).
- *
- * @return This routine does not return any value.
- *
- * @since XT 1.0
- */
-XTAPI
-VOID
-HlDisableLegacyPic(VOID)
-{
-    /* Mask all interrupts */
-    HlIoPortOutByte(PIC1_DATA_PORT, 0xFF);
-    HlIoPortOutByte(PIC2_DATA_PORT, 0xFF);
-}
-
 /**
  * Reads from the APIC register.
  *
@@ -179,9 +162,6 @@ HlpHandlePicSpuriousService(VOID)
 /**
  * Initializes the APIC interrupt controller.
  *
- * @param CpuNumber
- *        Supplies the number of the CPU, that is being initialized.
- *
  * @return This routine does not return any value.
  *
  * @since XT 1.0
@@ -288,10 +268,82 @@ HlpInitializeApic(VOID)
 }
 
 /**
- * Initializes the (A)PIC interrupt controller.
+ * Initializes the legacy PIC interrupt controller.
  *
- * @param CpuNumber
+ * @return This routine does not return any value.
- *        Supplies the number of the CPU, that is being initialized.
+ *
+ * @since XT 1.0
+ */
+XTAPI
+VOID
+HlpInitializeLegacyPic(VOID)
+{
+    PIC_I8259_ICW1 Icw1;
+    PIC_I8259_ICW2 Icw2;
+    PIC_I8259_ICW3 Icw3;
+    PIC_I8259_ICW4 Icw4;
+
+    /* Initialize ICW1 for PIC1 port */
+    Icw1.Init = TRUE;
+    Icw1.InterruptMode = LevelTriggered;
+    Icw1.InterruptVectorAddress = 0;
+    Icw1.Interval = Interval8;
+    Icw1.NeedIcw4 = TRUE;
+    Icw1.OperatingMode = Cascade;
+    HlIoPortOutByte(PIC1_CONTROL_PORT, Icw1.Bits);
+
+    /* Initialize ICW2 for PIC1 port */
+    Icw2.Bits = 0x00;
+    HlIoPortOutByte(PIC1_DATA_PORT, Icw2.Bits);
+
+    /* Initialize ICW3 for PIC1 port */
+    Icw3.Bits = 0;
+    Icw3.SlaveIrq2 = TRUE;
+    HlIoPortOutByte(PIC1_DATA_PORT, Icw3.Bits);
+
+    /* Initialize ICW4 for PIC1 port */
+    Icw4.BufferedMode = NonBuffered;
+    Icw4.EoiMode = NormalEoi;
+    Icw4.Reserved = 0;
+    Icw4.SpecialFullyNestedMode = FALSE;
+    Icw4.SystemMode = New8086Mode;
+    HlIoPortOutByte(PIC1_DATA_PORT, Icw4.Bits);
+
+    /* Mask all interrupts on PIC1 port */
+    HlIoPortOutByte(PIC1_DATA_PORT, 0xFF);
+
+    /* Initialize ICW1 for PIC2 port */
+    Icw1.Init = TRUE;
+    Icw1.InterruptMode = EdgeTriggered;
+    Icw1.InterruptVectorAddress = 0;
+    Icw1.Interval = Interval8;
+    Icw1.NeedIcw4 = TRUE;
+    Icw1.OperatingMode = Cascade;
+    HlIoPortOutByte(PIC2_CONTROL_PORT, Icw1.Bits);
+
+    /* Initialize ICW2 for PIC2 port */
+    Icw2.Bits = 0x08;
+    HlIoPortOutByte(PIC2_DATA_PORT, Icw2.Bits);
+
+    /* Initialize ICW3 for PIC2 port */
+    Icw3.Bits = 0;
+    Icw3.SlaveId = 2;
+    HlIoPortOutByte(PIC2_DATA_PORT, Icw3.Bits);
+
+    /* Initialize ICW4 for PIC2 port */
+    Icw4.BufferedMode = NonBuffered;
+    Icw4.EoiMode = NormalEoi;
+    Icw4.Reserved = 0;
+    Icw4.SpecialFullyNestedMode = FALSE;
+    Icw4.SystemMode = New8086Mode;
+    HlIoPortOutByte(PIC2_DATA_PORT, Icw4.Bits);
+
+    /* Mask all interrupts on PIC2 port */
+    HlIoPortOutByte(PIC2_DATA_PORT, 0xFF);
+}
+
+/**
+ * Initializes the (A)PIC interrupt controller.
  *
  * @return This routine does not return any value.
  *
@@ -303,7 +355,9 @@ XTAPI
 VOID
 HlpInitializePic(VOID)
 {
-    /* Disable legacy PIC and initialize APIC */
+    /* Initialize APIC */
-    HlDisableLegacyPic();
     HlpInitializeApic();
+
+    /* Initialize legacy PIC */
+    HlpInitializeLegacyPic();
 }

xtoskrnl/includes/amd64/hli.h

@@ -17,10 +17,6 @@ XTAPI
 VOID
 HlClearApicErrors(VOID);
 
-XTAPI
-VOID
-HlDisableLegacyPic(VOID);
-
 XTFASTCALL
 ULONG
 HlReadApicRegister(IN APIC_REGISTER Register);
@@ -50,6 +46,10 @@ XTAPI
 VOID
 HlpInitializeApic();
 
+XTAPI
+VOID
+HlpInitializeLegacyPic(VOID);
+
 XTAPI
 VOID
 HlpInitializePic();

xtoskrnl/includes/i686/hli.h

@@ -17,10 +17,6 @@ XTAPI
 VOID
 HlClearApicErrors(VOID);
 
-XTAPI
-VOID
-HlDisableLegacyPic(VOID);
-
 XTFASTCALL
 ULONG
 HlReadApicRegister(IN APIC_REGISTER Register);
@@ -50,6 +46,10 @@ XTAPI
 VOID
 HlpInitializeApic(VOID);
 
+XTAPI
+VOID
+HlpInitializeLegacyPic(VOID);
+
 XTAPI
 VOID
 HlpInitializePic(VOID);