From f46615f92ccdfb0548ef78a0d5356187438de275 Mon Sep 17 00:00:00 2001 From: belliash Date: Tue, 27 Dec 2022 23:19:33 +0100 Subject: [PATCH] Implement HlInvalidateTlbEntry(), HlReadModelSpecificRegister() and HlWriteModelSpecificRegister() routines --- sdk/xtdk/amd64/hlfuncs.h | 13 +++++++ sdk/xtdk/i686/hlfuncs.h | 13 +++++++ xtoskrnl/hl/amd64/cpufunc.c | 77 +++++++++++++++++++++++++++++++++++-- xtoskrnl/hl/i686/cpufunc.c | 71 ++++++++++++++++++++++++++++++++-- 4 files changed, 166 insertions(+), 8 deletions(-) diff --git a/sdk/xtdk/amd64/hlfuncs.h b/sdk/xtdk/amd64/hlfuncs.h index 4d39b32..0fd872c 100644 --- a/sdk/xtdk/amd64/hlfuncs.h +++ b/sdk/xtdk/amd64/hlfuncs.h @@ -30,6 +30,10 @@ XTCDECL VOID HlHalt(); +XTCDECL +VOID +HlInvalidateTlbEntry(IN PVOID Address); + XTCDECL UCHAR HlIoPortInByte(IN USHORT Port); @@ -61,6 +65,10 @@ XTCDECL ULONG_PTR HlReadControlRegister(IN USHORT ControlRegister); +XTCDECL +ULONGLONG +HlReadModelSpecificRegister(IN ULONG Register); + XTCDECL VOID HlSetInterruptFlag(); @@ -70,4 +78,9 @@ VOID HlWriteControlRegister(IN USHORT ControlRegister, IN UINT_PTR Value); +XTCDECL +VOID +HlWriteModelSpecificRegister(IN ULONG Register, + IN ULONGLONG Value); + #endif /* __XTDK_AMD64_HLFUNCS_H */ diff --git a/sdk/xtdk/i686/hlfuncs.h b/sdk/xtdk/i686/hlfuncs.h index a4265e4..cf6137d 100644 --- a/sdk/xtdk/i686/hlfuncs.h +++ b/sdk/xtdk/i686/hlfuncs.h @@ -30,6 +30,10 @@ XTCDECL VOID HlHalt(); +XTCDECL +VOID +HlInvalidateTlbEntry(IN PVOID Address); + XTCDECL UCHAR HlIoPortInByte(IN USHORT Port); @@ -61,6 +65,10 @@ XTCDECL ULONG_PTR HlReadControlRegister(IN USHORT ControlRegister); +XTCDECL +ULONGLONG +HlReadModelSpecificRegister(IN ULONG Register); + XTCDECL VOID HlSetInterruptFlag(); @@ -70,4 +78,9 @@ VOID HlWriteControlRegister(IN USHORT ControlRegister, IN UINT_PTR Value); +XTCDECL +VOID +HlWriteModelSpecificRegister(IN ULONG Register, + IN ULONGLONG Value); + #endif /* __XTDK_I686_HLFUNCS_H */ diff --git a/xtoskrnl/hl/amd64/cpufunc.c b/xtoskrnl/hl/amd64/cpufunc.c index ea4b0d9..1197ebc 100644 --- a/xtoskrnl/hl/amd64/cpufunc.c +++ b/xtoskrnl/hl/amd64/cpufunc.c @@ -76,10 +76,27 @@ XTCDECL VOID HlHalt() { - while(TRUE) - { - asm volatile("hlt"); - } + asm volatile("hlt"); +} + +/** + * Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address. + * + * @param Address + * Suuplies a virtual address whose associated TLB entry will be invalidated. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlInvalidateTlbEntry(IN PVOID Address) +{ + asm volatile("invlpg (%0)" + : + : "b"(Address) + : "memory"); } /** @@ -280,6 +297,30 @@ HlReadControlRegister(IN USHORT ControlRegister) return Value; } +/** + * Reads a 64-bit value from the requested Model Specific Register (MSR). + * + * @param Register + * Supplies the MSR to read. + * + * @return This routine returns the 64-bit MSR value. + * + * @since XT 1.0 + */ +XTCDECL +ULONGLONG +HlReadModelSpecificRegister(IN ULONG Register) +{ + ULONG Low, High; + + asm volatile("rdmsr" + : "=a"(Low), + "=d"(High) + : "c"(Register)); + + return ((ULONGLONG)High << 32) | Low; +} + /** * Instructs the processor to set the interrupt flag. * @@ -352,3 +393,31 @@ HlWriteControlRegister(IN USHORT ControlRegister, break; } } + +/** + * Writes a 64-bit value to the requested Model Specific Register (MSR). + * + * @param Register + * Supplies the MSR register to write. + * + * @param Value + * Supplies the 64-bit value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlWriteModelSpecificRegister(IN ULONG Register, + IN ULONGLONG Value) +{ + ULONG Low = Value & 0xFFFFFFFF; + ULONG High = Value >> 32; + + asm volatile("wrmsr" + : + : "c"(Register), + "a"(Low), + "d"(High)); +} diff --git a/xtoskrnl/hl/i686/cpufunc.c b/xtoskrnl/hl/i686/cpufunc.c index b0126cd..4f45ee8 100644 --- a/xtoskrnl/hl/i686/cpufunc.c +++ b/xtoskrnl/hl/i686/cpufunc.c @@ -76,10 +76,27 @@ XTCDECL VOID HlHalt() { - while(TRUE) - { - asm volatile("hlt"); - } + asm volatile("hlt"); +} + +/** + * Invalidates the TLB (Translation Lookaside Buffer) for specified virtual address. + * + * @param Address + * Suuplies a virtual address whose associated TLB entry will be invalidated. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlInvalidateTlbEntry(PVOID Address) +{ + asm volatile("invlpg (%0)" + : + : "b"(Address) + : "memory"); } /** @@ -274,6 +291,28 @@ HlReadControlRegister(IN USHORT ControlRegister) return Value; } +/** + * Reads a 64-bit value from the requested Model Specific Register (MSR). + * + * @param Register + * Supplies the MSR to read. + * + * @return This routine returns the 64-bit MSR value. + * + * @since XT 1.0 + */ +XTCDECL +ULONGLONG +HlReadModelSpecificRegister(IN ULONG Register) +{ + ULONGLONG Value; + + asm volatile("rdmsr" + : "=A" (Value) + : "c" (Register)); + return Value; +} + /** * Instructs the processor to set the interrupt flag. * @@ -339,3 +378,27 @@ HlWriteControlRegister(IN USHORT ControlRegister, break; } } + +/** + * Writes a 64-bit value to the requested Model Specific Register (MSR). + * + * @param Register + * Supplies the MSR register to write. + * + * @param Value + * Supplies the 64-bit value to write. + * + * @return This routine does not return any value. + * + * @since XT 1.0 + */ +XTCDECL +VOID +HlWriteModelSpecificRegister(IN ULONG Register, + IN ULONGLONG Value) +{ + asm volatile("wrmsr" + : + : "c" (Register), + "A" (Value)); +}