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Adapt i686 memory mapping to new PML3 types
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This commit is contained in:
Aiken Harris 2025-08-16 00:36:20 +02:00
parent 22f81a106b
commit f85fe31b38
Signed by: harraiken
GPG Key ID: C40F06CB7493C1F5
1 changed files with 13 additions and 13 deletions
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26
xtldr/arch/i686/memory.c
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@ -61,9 +61,9 @@ BlBuildPageMap(IN PXTBL_PAGE_MAPPING PageMap,
/* Fill the PDPT with pointers to the Page Directories */ /* Fill the PDPT with pointers to the Page Directories */
for(Index = 0; Index < 4; Index++) for(Index = 0; Index < 4; Index++)
{ {
RtlZeroMemory(&((PHARDWARE_PTE)PageMap->PtePointer)[Index], sizeof(HARDWARE_PTE)); RtlZeroMemory(&((PHARDWARE_MODERN_PTE)PageMap->PtePointer)[Index], sizeof(HARDWARE_MODERN_PTE));
((PHARDWARE_PTE)PageMap->PtePointer)[Index].PageFrameNumber = DirectoryAddress / EFI_PAGE_SIZE; ((PHARDWARE_MODERN_PTE)PageMap->PtePointer)[Index].PageFrameNumber = DirectoryAddress / EFI_PAGE_SIZE;
((PHARDWARE_PTE)PageMap->PtePointer)[Index].Valid = 1; ((PHARDWARE_MODERN_PTE)PageMap->PtePointer)[Index].Valid = 1;
DirectoryAddress += EFI_PAGE_SIZE; DirectoryAddress += EFI_PAGE_SIZE;
} }
} }
@ -193,8 +193,8 @@ BlMapPage(IN PXTBL_PAGE_MAPPING PageMap,
SIZE_T PageFrameNumber; SIZE_T PageFrameNumber;
PVOID Pml1, Pml2, Pml3; PVOID Pml1, Pml2, Pml3;
SIZE_T Pml1Entry, Pml2Entry, Pml3Entry; SIZE_T Pml1Entry, Pml2Entry, Pml3Entry;
PHARDWARE_PTE PmlTable;
PHARDWARE_LEGACY_PTE LegacyPmlTable; PHARDWARE_LEGACY_PTE LegacyPmlTable;
PHARDWARE_MODERN_PTE PmlTable;
EFI_STATUS Status; EFI_STATUS Status;
/* Set the Page Frame Number (PFN) */ /* Set the Page Frame Number (PFN) */
@ -231,8 +231,8 @@ BlMapPage(IN PXTBL_PAGE_MAPPING PageMap,
} }
/* Set the 64-bit PTE entry */ /* Set the 64-bit PTE entry */
PmlTable = (PHARDWARE_PTE)Pml1; PmlTable = (PHARDWARE_MODERN_PTE)Pml1;
RtlZeroMemory(&PmlTable[Pml1Entry], sizeof(HARDWARE_PTE)); RtlZeroMemory(&PmlTable[Pml1Entry], sizeof(HARDWARE_MODERN_PTE));
PmlTable[Pml1Entry].PageFrameNumber = PageFrameNumber; PmlTable[Pml1Entry].PageFrameNumber = PageFrameNumber;
PmlTable[Pml1Entry].Valid = 1; PmlTable[Pml1Entry].Valid = 1;
PmlTable[Pml1Entry].Writable = 1; PmlTable[Pml1Entry].Writable = 1;
@ -304,14 +304,14 @@ BlpGetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
ULONGLONG PmlPointer = 0; ULONGLONG PmlPointer = 0;
EFI_STATUS Status; EFI_STATUS Status;
PHARDWARE_LEGACY_PTE LegacyPmlTable; PHARDWARE_LEGACY_PTE LegacyPmlTable;
PHARDWARE_PTE PmlTable; PHARDWARE_MODERN_PTE PmlTable;
BOOLEAN ValidPte = FALSE; BOOLEAN ValidPte = FALSE;
/* Check page map level to determine PTE size */ /* Check page map level to determine PTE size */
if(PageMap->PageMapLevel >= 3) if(PageMap->PageMapLevel >= 3)
{ {
/* 64-bit PTE for PML3 (PAE enabled) */ /* 64-bit PTE for PML3 (PAE enabled) */
PmlTable = (PHARDWARE_PTE)PageTable; PmlTable = (PHARDWARE_MODERN_PTE)PageTable;
if(PmlTable[Entry].Valid) if(PmlTable[Entry].Valid)
{ {
/* Get page frame number from page table entry */ /* Get page frame number from page table entry */
@ -362,7 +362,7 @@ BlpGetNextPageTable(IN PXTBL_PAGE_MAPPING PageMap,
if(PageMap->PageMapLevel >= 3) if(PageMap->PageMapLevel >= 3)
{ {
/* 64-bit PTE for PML3 (PAE enabled) */ /* 64-bit PTE for PML3 (PAE enabled) */
PmlTable = (PHARDWARE_PTE)PageTable; PmlTable = (PHARDWARE_MODERN_PTE)PageTable;
PmlTable[Entry].PageFrameNumber = Address / EFI_PAGE_SIZE; PmlTable[Entry].PageFrameNumber = Address / EFI_PAGE_SIZE;
PmlTable[Entry].Valid = 1; PmlTable[Entry].Valid = 1;
PmlTable[Entry].Writable = 1; PmlTable[Entry].Writable = 1;
@ -406,7 +406,7 @@ BlpSelfMapPml(IN PXTBL_PAGE_MAPPING PageMap,
IN ULONG_PTR SelfMapAddress) IN ULONG_PTR SelfMapAddress)
{ {
PHARDWARE_LEGACY_PTE LegacyPml; PHARDWARE_LEGACY_PTE LegacyPml;
PHARDWARE_PTE Pml; PHARDWARE_MODERN_PTE Pml;
ULONGLONG PmlIndex; ULONGLONG PmlIndex;
ULONG Index; ULONG Index;
@ -417,13 +417,13 @@ BlpSelfMapPml(IN PXTBL_PAGE_MAPPING PageMap,
PmlIndex = (SelfMapAddress >> MM_PDI_SHIFT) & 0x1FF; PmlIndex = (SelfMapAddress >> MM_PDI_SHIFT) & 0x1FF;
/* Get Page Directory */ /* Get Page Directory */
Pml = (PHARDWARE_PTE)(((PHARDWARE_PTE)PageMap->PtePointer)[SelfMapAddress >> MM_PPI_SHIFT].PageFrameNumber * EFI_PAGE_SIZE); Pml = (PHARDWARE_MODERN_PTE)(((PHARDWARE_MODERN_PTE)PageMap->PtePointer)[SelfMapAddress >> MM_PPI_SHIFT].PageFrameNumber * EFI_PAGE_SIZE);
/* Add self-mapping for PML3 (PAE enabled) */ /* Add self-mapping for PML3 (PAE enabled) */
for(Index = 0; Index < 4; Index++) for(Index = 0; Index < 4; Index++)
{ {
RtlZeroMemory(&Pml[PmlIndex + Index], sizeof(HARDWARE_PTE)); RtlZeroMemory(&Pml[PmlIndex + Index], sizeof(HARDWARE_MODERN_PTE));
Pml[PmlIndex + Index].PageFrameNumber = ((PHARDWARE_PTE)PageMap->PtePointer)[Index].PageFrameNumber; Pml[PmlIndex + Index].PageFrameNumber = ((PHARDWARE_MODERN_PTE)PageMap->PtePointer)[Index].PageFrameNumber;
Pml[PmlIndex + Index].Valid = 1; Pml[PmlIndex + Index].Valid = 1;
Pml[PmlIndex + Index].Writable = 1; Pml[PmlIndex + Index].Writable = 1;
} }