Add more intrinsic routines
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@@ -97,7 +97,7 @@ HlInvalidateTlbEntry(PVOID Address)
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{
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asm volatile("invlpg (%0)"
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:
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: "b"(Address)
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: "b" (Address)
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: "memory");
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}
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@@ -117,8 +117,8 @@ HlIoPortInByte(IN USHORT Port)
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{
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UCHAR Value;
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asm volatile("inb %1, %0"
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: "=a"(Value)
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: "Nd"(Port));
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: "=a" (Value)
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: "Nd" (Port));
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return Value;
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}
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@@ -138,8 +138,8 @@ HlIoPortInShort(IN USHORT Port)
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{
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USHORT Value;
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asm volatile("inw %1, %0"
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: "=a"(Value)
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: "Nd"(Port));
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: "=a" (Value)
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: "Nd" (Port));
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return Value;
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}
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@@ -159,8 +159,8 @@ HlIoPortInLong(IN USHORT Port)
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{
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ULONG Value;
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asm volatile("inl %1, %0"
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: "=a"(Value)
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: "Nd"(Port));
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: "=a" (Value)
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: "Nd" (Port));
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return Value;
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}
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@@ -184,8 +184,8 @@ HlIoPortOutByte(IN USHORT Port,
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{
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asm volatile("outb %0, %1"
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:
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: "a"(Value),
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"Nd"(Port));
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: "a" (Value),
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"Nd" (Port));
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}
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/**
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@@ -208,8 +208,8 @@ HlIoPortOutShort(IN USHORT Port,
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{
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asm volatile("outw %0, %1"
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:
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: "a"(Value),
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"Nd"(Port));
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: "a" (Value),
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"Nd" (Port));
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}
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/**
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@@ -232,8 +232,8 @@ HlIoPortOutLong(IN USHORT Port,
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{
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asm volatile("outl %0, %1"
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:
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: "a"(Value),
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"Nd"(Port));
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: "a" (Value),
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"Nd" (Port));
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}
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/**
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@@ -329,7 +329,7 @@ HlReadTimeStampCounter()
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ULONGLONG Value;
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asm volatile("rdtsc"
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: "=A"(Value));
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: "=A" (Value));
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return Value;
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}
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@@ -348,6 +348,116 @@ HlSetInterruptFlag()
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asm volatile("sti");
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}
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/**
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* Stores GDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where GDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreGlobalDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sgdt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores IDT register into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where IDT will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreInterruptDescriptorTable(OUT PVOID Destination)
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{
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asm volatile("sidt %0"
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:
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: "m" (*(PSHORT)Destination)
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: "memory");
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}
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/**
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* Stores specified segment into the given memory area.
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*
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* @param Segment
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* Supplies a segment identification.
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*
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* @param Destination
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* Supplies a pointer to the memory area where segment data will be stored.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreSegment(IN USHORT Segment,
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OUT PVOID Destination)
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{
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switch(Segment)
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{
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case SEGMENT_CS:
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asm volatile("movl %%cs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_DS:
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asm volatile("movl %%ds, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_ES:
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asm volatile("movl %%es, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_FS:
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asm volatile("movl %%fs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_GS:
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asm volatile("movl %%gs, %0"
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: "=r" (*(PUINT)Destination));
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break;
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case SEGMENT_SS:
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asm volatile("movl %%ss, %0"
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: "=r" (*(PUINT)Destination));
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break;
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default:
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Destination = NULL;
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break;
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}
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}
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/**
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* Stores TR into the given memory area.
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*
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* @param Destination
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* Supplies a pointer to the memory area where TR will be stores.
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*
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* @return This routine does not return any value.
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*
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* @since XT 1.0
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*/
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XTCDECL
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VOID
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HlStoreTaskRegister(OUT PVOID Destination)
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{
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asm volatile("str %0"
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:
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: "m" (*(PULONG)Destination)
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: "memory");
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}
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/**
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* Writes a value to the specified CPU control register.
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*
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@@ -373,28 +483,28 @@ HlWriteControlRegister(IN USHORT ControlRegister,
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/* Write value to CR0 */
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asm volatile("mov %0, %%cr0"
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:
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: "r"(Value)
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: "r" (Value)
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: "memory");
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break;
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case 2:
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/* Write value to CR2 */
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asm volatile("mov %0, %%cr2"
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:
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: "r"(Value)
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: "r" (Value)
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: "memory");
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break;
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case 3:
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/* Write value to CR3 */
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asm volatile("mov %0, %%cr3"
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:
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: "r"(Value)
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: "r" (Value)
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: "memory");
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break;
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case 4:
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/* Write value to CR4 */
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asm volatile("mov %0, %%cr4"
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:
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: "r"(Value)
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: "r" (Value)
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: "memory");
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break;
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}
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